單片機外文翻譯--at89s52單片機

1、<p>　　AT89S52英文資料及中文翻譯</p><p><b>　　AT89S52</b></p><p><b>　　Features</b></p><p>　　? Compatible with MCS-51 Products</p><p>　　? 8K Bytes of I

2、n-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase Cycles</p><p>　　? 4.0V to 5.5V Operating Range</p><p>　　? Fully Static Operation: 0 Hz to 33 MHz</p><p>　　?

3、Three-level Program Memory Lock </p><p>　　? 256 x 8-bit Internal RAM </p><p>　　? 32 Programmable I/O Lines </p><p>　　? Three 16-bit Timer/Counters </p><p>　　? Eight Int

4、errupt Sources</p><p>　　? Full Duplex UART Serial Channel </p><p>　　? Low-power Idle and Power-down Modes</p><p>　　? Interrupt Recovery from Power-down Mode </p><p>　　?

5、 Watchdog Timer ? Dual Data Pointer </p><p>　　? Power-off Flag ? Fast Programming Time </p><p>　　? Flexible ISP Programming (Byte and Page Mode) </p><p>　　? Green (Pb/Halide-free) P

6、ackaging Option</p><p>　　Description</p><p>　　The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufact

7、ured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by

8、 a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic</p><p>　　The AT89S52 provides the following standard features: 8K bytes of

9、 Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. I

10、n addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,</

11、p><p>　　Pin Description</p><p>　　2.1 VCC ：Supply voltage.</p><p>　　2.2 GND ：Ground.</p><p>　　2.3 Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output

12、port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses

13、to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. Externa</p><p&

14、gt;　　2.4 Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-

15、ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter

16、2 external count input (P1.0/T2) and the timer/counter 2 trigger </p><p>　　Port 1 also receives the low-order address bytes during Flash programming and verification.</p><p>　　2.5 Port 2：Port 2

17、is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as

18、inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur

19、-ing accesses to external data memory that</p><p>　　2.6 Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written

20、 to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives so

21、me control signals for Flash programming and verification. Port 3 also serves the functions of various special features of th</p><p>　　2.7 RST：Reset input. A high on this pin for two machine cycles while the

22、 oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of

23、 bit DISRTO, the RESET HIGH out feature is enabled.</p><p>　　2.8 ALE/：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is al

24、so the program pulse input () during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that

25、 one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of S</p><p>　　2.9 ：Program Store Enable () is the read strobe to external pro

26、gram memory. When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, except that two activations are skipped during each access to exter-nal data memory.</p><p

27、>　　2.10 /VPP：External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is prog

28、rammed, will be internally latched on reset. should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.</p><p>

29、　　2.11 XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p><p>　　2.12 XTAL2：Output from the inverting oscillator amplifier.</p><p>　　Memory Or

30、ganization</p><p>　　MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.</p><p>　　3.1 Program Memo

31、ry</p><p>　　If the pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to int

32、ernal memory and fetches to addresses 2000H through FFFFH are to external memory.</p><p>　　3.2 Data Memory</p><p>　　The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a

33、parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal

34、location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the S</p><p&

35、gt;　　MOV 0A0H, #data</p><p>　　Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the dat

36、a byte at address 0A0H, rather than P2 (whose address is 0A0H).</p><p>　　MOV @R0, #data</p><p>　　Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RA

37、M are available as stack space.</p><p>　　Watchdog Timer (One-time Enabled with Reset-out)</p><p>　　The WDT is intended as a recovery method in situations where the CPU may be subjected to softwa

38、re upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST

39、register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock f</p><p>　　4.1 Using th

40、e WDT</p><p>　　To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDT

41、RST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. Thi

42、s means the user must reset the WDT at least every 16383 machine cycles. To reset the WD</p><p>　　4.2 WDT During Power-down and Idle</p><p>　　In Power-down mode the oscillator stops, which means

43、 the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled

44、 prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly d

45、ifferent</p><p><b>　　5. UART</b></p><p>　　The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please

46、click on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF</p><p>　　6. Timer 0 and 1</p><p>　　Timer 0 and Timer 1 in the AT89S52 opera

47、te the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_

48、documents/DOC4316.PDF</p><p>　　7. Timer 2</p><p>　　Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/ in the S

49、FR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, T

50、H2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator pe</p><p>　　Table 6-1. Timer 2 Operating Modes</p><p>　　In

51、 the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When

52、 the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Si

53、nce two machine cycles (24 oscillator periods) are require</p><p>　　7.1 Capture Mode</p><p>　　In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-b

54、it timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also c

55、auses the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, li</p><p>　　7.2 Auto-reload (

56、Up or Down Counter)</p><p>　　Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2M

57、OD . Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0.

58、 In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFF</p><p>　　8. Baud Rate Generator</p><p>　　Timer 2 is selected as the baud rate generator by

59、setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCL

60、K puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers

61、RCAP2H and</p><p>　　The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/ = 0). The timer operation is different for Timer 2 when

62、 it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator f

63、requency). The baud rate formula is given below.</p><p>　　where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.</p><p>　　This figure is valid only if RCL

64、K or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H

65、, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2

66、 or TL2 should not be read f</p><p>　　9. Programmable Clock Out</p><p>　　A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alterna

67、te functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a

68、 clock generator, bit C/ (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency dep</p><p>　　In the clock-out mode, Timer 2 roll-o

69、vers will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however,

70、 that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.</p><p>　　10. Interrupts</p><p>　　The AT89S52 has a total

71、 of six interrupt vectors: two external interrupts ( and ), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting o

72、r clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this

73、 bit position, since it may be used i</p><p>　　11. Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured f

74、or use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirem

75、ents on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage</p><p>　　12. Idle Mode</p>

76、;<p>　　In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain un

77、changed during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from w

78、here it left off, up to two machine cycles before the internal reset algor</p><p>　　13. Power-down Mode</p><p>　　In the Power-down mode, the oscillator is stopped, and the instruction that invo

79、kes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware

80、 reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and mus</p><p>

81、;　　AT89S52單片機</p><p><b>　　主要性能</b></p><p>　　? 與MCS-51單片機產(chǎn)品兼容</p><p>　　? 8K字節(jié)在系統(tǒng)可編程Flash存儲器</p><p>　　? 1000次擦寫周期</p><p>　　? 全靜態(tài)操作：0Hz～33Hz</p

82、><p>　　? 三級加密程序存儲器</p><p>　　? 32個可編程I/O口線</p><p>　　? 三個16位定時器/計數(shù)器</p><p><b>　　? 八個中斷源</b></p><p>　　? 全雙工UART串行通道</p><p>　　? 低功耗空閑和掉電模

83、式</p><p>　　? 掉電后中斷可喚醒</p><p><b>　　? 看門狗定時器</b></p><p><b>　　? 雙數(shù)據(jù)指針</b></p><p><b>　　? 掉電標識符</b></p><p><b>　　功能特征描述

84、</b></p><p>　　AT89S52是一種低功耗、高性能CMOS8位微控制器，具有8K 在系統(tǒng)可編程Flash 存儲器。使用Atmel 公司高密度非易失性存儲器技術(shù)制造，與工業(yè)80C51 產(chǎn)品指令和引腳完全兼容。片上Flash允許程序存儲器在系統(tǒng)可編程，亦適于常規(guī)編程器。在單芯片上，擁有靈巧的8 位CPU 和在系統(tǒng)可編程Flash，使得AT89S52為眾多嵌入式控制應(yīng)用系統(tǒng)提供高靈活、超有效的

85、解決方案。AT89S52具有以下標準功能： 8k字節(jié)Flash，256字節(jié)RAM，32 位I/O 口線，看門狗定時器，2 個數(shù)據(jù)指針，三個16 位定時器/計數(shù)器，一個6向量2級中斷結(jié)構(gòu)，全雙工串行口，片內(nèi)晶振及時鐘電路。另外，AT89S52 可降至0Hz 靜態(tài)邏輯操作，支持2種軟件可選擇節(jié)電模式?？臻e模式下，CPU停止工作，允許RAM、定時器/計數(shù)器、串口、中斷繼續(xù)工作。掉電保護方式下，RAM內(nèi)容被保存，振蕩器被凍結(jié)，單片機一切工作停止

86、，直到下一個中斷或硬件復(fù)位為止。</p><p><b>　　引腳功能</b></p><p><b>　　VCC ：電源</b></p><p><b>　　GND: 接地</b></p><p>　　P0口： P0口是一個8位漏極開路的雙向I/O口。作為輸出口，每位能驅(qū)動8

87、個TTL邏輯電平。對P0端口寫“1”時，引腳用作高阻抗輸入。當訪問外部程序和數(shù)據(jù)存儲器時，P0口也被作為低8位地址/數(shù)據(jù)復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。在flash編程時，P0口也用來接收指令字節(jié)；在程序校驗時，輸出指令字節(jié)。程序校驗時，需要外部上拉電阻。</p><p>　　2.4 P1口：P1 口是一個具有內(nèi)部上拉電阻的8 位雙向I/O 口，p1 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P1 端

88、口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。此外，P1.0和P1.2分別作定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和時器/計數(shù)器2的觸發(fā)輸入（P1.1/T2EX），具體如下表所示。在flash編程和校驗時，P1口接收低8位地址字節(jié)。</p><p>　　2.5 P2口：P2 口是一個具有內(nèi)部上拉電阻的8 位雙向I

89、/O 口，P2 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P2 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器或用16位地址讀取外部數(shù)據(jù)存儲器（例如執(zhí)行MOVX @DPTR）時，P2 口送出高八位地址。在這種應(yīng)用中，P2 口使用很強的內(nèi)部上拉發(fā)送1。在使用8位地址（如MOVX @RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2鎖存器

90、的內(nèi)容。在flash編程和校驗時，P2口也接收高8位地址字節(jié)和一些控制信號。</p><p>　　2.6 P3口：P3 口是一個有內(nèi)部上拉電阻的8 位雙向I/O 口，p2 輸出緩沖器能驅(qū)動4 個TTL 邏輯電平。對P3 端口寫“1”時，內(nèi)部上拉電阻把端口拉高，此時可以作為輸入口使用。作為輸入使用時，被外部拉低的引腳由于內(nèi)部電阻的原因，將輸出電流（IIL）。P3口亦作為AT89S52特殊功能（第二功能）使用，如下

91、表所示。在flash編程和校驗時，P3口也接收一些控制信號。</p><p>　　2.7 RST：復(fù)位輸入。晶振工作時，RST腳持續(xù)2 個機器周期高電平將使單片機復(fù)位。看門狗計時完成后，RST 腳輸出96 個晶振周期的高電平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復(fù)位高電平有效。</p><p>　　2.8 ALE/：地址鎖存控制信號（

92、ALE）是訪問外部程序存儲器時，鎖存低8 位地址的輸出脈沖。在flash編程時，此引腳()也用作編程輸入脈沖。在一般情況下，ALE 以晶振六分之一的固定頻率輸出脈沖，可用來作為外部定時器或時鐘使用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖將會跳過。如果需要，通過將地址為8EH的SFR的第0位置 “1”，ALE操作將無效。這一位置 “1”，ALE 僅在執(zhí)行MOVX 或MOVC指令時有效。否則，ALE 將被微弱拉高。這個ALE

93、 使能標志位（地址為8EH的SFR的第0位）的設(shè)置對微控制器處于外部執(zhí)行模式下無效。</p><p>　　2.9 ：外部程序存儲器選通信號()是外部程序存儲器選通信號。當AT89S52從外部程序存儲器執(zhí)行外部代碼時，在每個機器周期被激活兩次，而在訪問外部數(shù)據(jù)存儲器時，將不被激活。</p><p>　　2.10 /VPP：訪問外部程序存儲器控制信號。為使能從0000H 到FFFFH的外部程序

94、存儲器讀取指令，必須接GND。為了執(zhí)行內(nèi)部程序指令，應(yīng)該接VCC。在flash編程期間，也接收12伏VPP電壓。</p><p>　　2.11 XTAL1：振蕩器反相放大器和內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　2.12 XTAL2：振蕩器反相放大器的輸出端。</p><p><b>　　3. 存儲器結(jié)構(gòu)</b></p>

95、<p>　　MCS-51器件有單獨的程序存儲器和數(shù)據(jù)存儲器。外部程序存儲器和數(shù)據(jù)存儲器都可以64K尋址。</p><p>　　3.1 程序存儲器: 如果引腳接地，程序讀取只從外部存儲器開始。對于89S52，如果 接VCC，程序讀寫先從內(nèi)部存儲器（地址為0000H～1FFFH）開始，接著從外部尋址，尋址地址為：2000H~FFFFH。</p><p>　　3.2 數(shù)據(jù)存儲器: A

96、T89S52 有256 字節(jié)片內(nèi)數(shù)據(jù)存儲器。高128 字節(jié)與特殊功能寄存器重疊。也就是說高128字節(jié)與特殊功能寄存器有相同的地址，而物理上是分開的。當一條指令訪問高于7FH 的地址時，尋址方式?jīng)Q定CPU 訪問高128 字節(jié)RAM 還是特殊功能寄存器空間。直接尋址方式訪問特殊功能寄存器（SFR）。例如，下面的直接尋址指令訪問0A0H（P2口）存儲單元</p><p>　　MOV 0A0H , #data</p

97、><p>　　使用間接尋址方式訪問高128 字節(jié)RAM。例如，下面的間接尋址方式中，R0 內(nèi)容為0A0H，訪問的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。</p><p>　　MOV @R0 , #data</p><p>　　堆棧操作也是簡介尋址方式。因此，高128字節(jié)數(shù)據(jù)RAM也可用于堆?？臻g。</p><p><b

98、>　　4. 看門狗定時器</b></p><p>　　WDT是一種需要軟件控制的復(fù)位方式。WDT 由13位計數(shù)器和特殊功能寄存器中的看門狗定時器復(fù)位存儲器（WDTRST）構(gòu)成。WDT 在默認情況下無法工作；為了激活WDT，戶用必須往WDTRST 寄存器（地址：0A6H）中依次寫入01EH 和0E1H。當WDT激活后，晶振工作，WDT在每個機器周期都會增加。WDT計時周期依賴于外部時鐘頻率。除了復(fù)

99、位（硬件復(fù)位或WDT溢出復(fù)位），沒有辦法停止WDT工作。當WDT溢出，它將驅(qū)動RSR引腳一個高個電平輸出。</p><p>　　4.1 WDT的使用</p><p>　　為了激活WDT，用戶必須向WDTRST寄存器（地址為0A6H的SFR）依次寫入0E1H和0E1H。當WDT激活后，用戶必須向WDTRST寫入01EH和0E1H喂狗來避免WDT溢出。當計數(shù)達到8191(1FFFH)時，13

100、位計數(shù)器將會溢出，這將會復(fù)位器件。晶振正常工作、WDT激活后，每一個機器周期WDT 都會增加。為了復(fù)位WDT，用戶必須向WDTRST 寫入01EH 和0E1H（WDTRST 是只讀寄存器）。WDT 計數(shù)器不能讀或?qū)?。當WDT 計數(shù)器溢出時，將給RST 引腳產(chǎn)生一個復(fù)位脈沖輸出，這個復(fù)位脈沖持續(xù)96個晶振周期（TOSC），其中TOSC=1/FOSC。為了很好地使用WDT，應(yīng)該在一定時間內(nèi)周期性寫入那部分代碼，以避免WDT復(fù)位。</p

101、><p>　　4.2 掉電和空閑方式下的WDT</p><p>　　在掉電模式下，晶振停止工作，這意味這WDT也停止了工作。在這種方式下，用戶不必喂狗。有兩種方式可以離開掉電模式：硬件復(fù)位或通過一個激活的外部中斷。通過硬件復(fù)位退出掉電模式后，用戶就應(yīng)該給WDT 喂狗，就如同通常AT89S52 復(fù)位一樣。通過中斷退出掉電模式的情形有很大的不同。中斷應(yīng)持續(xù)拉低很長一段時間，使得晶振穩(wěn)定。當中斷拉高

102、后，執(zhí)行中斷服務(wù)程序。為了防止WDT在中斷保持低電平的時候復(fù)位器件，WDT 直到中斷拉低后才開始工作。這就意味著WDT 應(yīng)該在中斷服務(wù)程序中復(fù)位。為了確保在離開掉電模式最初的幾個狀態(tài)WDT不被溢出，最好在進入掉電模式前就復(fù)WDT。在進入待機模式前，特殊寄存器AUXR的WDIDLE位用來決定WDT是否繼續(xù)計數(shù)。默認狀態(tài)下，在待機模式下，WDIDLE＝0，WDT繼續(xù)計數(shù)。為了防止WDT在待機模式下復(fù)位AT89S52，用戶應(yīng)該建立一個定時器，