外文資料翻譯 --at89s52單片機簡介

1、<p><b>　　外文文獻及翻譯</b></p><p>　　A brief introduction of AT89S52</p><p>　　2.Pin Description</p><p>　　2.1 VCC: Supply voltage.</p><p>　　2.2 GND: Ground.<

2、;/p><p>　　2.3 Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inpu

3、ts. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during F

4、lash programming and outputs the code bytes during program verification. Externa</p><p>　　2.4 Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/sour

5、ce four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pulled-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) bec

6、ause of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigge</p><p>　　Port 1 also receives the low-order

7、 address bytes during Flash programming and verification.</p><p>　　2.5 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. Whe

8、n 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) Because of the internal pull

9、-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that </p><p>　　2.6 Port 3: Port 3 is an 8-bit bidirectional I/O port wit

10、h internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are

11、 externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of

12、 th</p><p>　　2.7 RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. Th

13、e DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.</p><p>　　2.8 ALE/: Address Latch Enable (ALE) is an outp

14、ut pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input () during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 th

15、e oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setti

16、ng bit 0 or S</p><p>　　2.9 : Program Store Enable () is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, is activated twice each machine cycle, ex

17、cept that two activations are skipped during each access to external data memory.</p><p>　　2.10 /VPP: External Access Enable. must be strapped to GND in order to enable the device to fetch code from extern

18、al program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, will be internally latched on reset. should be strapped to VCC for internal program executions. This pin also

19、receives the 12-volt programming enable voltage (VPP) during Flash programming.</p><p>　　2.11 XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.</p>

20、<p>　　2.12 XTAL2: Output from the inverting oscillator amplifier.</p><p>　　3.Memory Organization</p><p>　　MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K

21、 bytes each of external Program and Data Memory can be addressed.</p><p>　　3.1 Program Memory</p><p>　　If the EA pin is connected to GND, all program fetches are directed to external memory. On

22、the AT89S52, if is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.</p><p>　　3.2 Data M

23、emory</p><p>　　The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addres

24、ses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper

25、128 bytes of RAM or the SFR space. Instructions which use direct addressing access the S</p><p>　　MOV 0A0H, #data</p><p>　　Instructions that use indirect addressing access the upper 128 bytes of

26、 RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).</p><p>　　MOV @R0, #data</p>&l

27、t;p>　　Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.</p><p>　　4.Watchdog Timer (One-time Enabled with Reset-out)</p>

28、<p>　　The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted

29、to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillato

30、r is running. The WDT timeout period is dependent on the external clock f</p><p><b>　　5.UART</b></p><p>　　The UART in the AT89S52 operates the same way as the UART in the AT89C51 and

31、 AT89C52. For further information on the UART operation, please click on the document link below:</p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF</p><p>　　6.Timer 0 and 1&

32、lt;/p><p>　　Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:&

33、lt;/p><p>　　http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF</p><p><b>　　7.Timer 2</b></p><p>　　Timer 2 is a 16-bit Timer/Counter that can operate as either a

34、timer or an event counter. The type of operation is selected by bit C/ in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by b

35、its in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator pe<

36、;/p><p>　　Table 6-1 Timer 2 Operating Modes</p><p>　　In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this fun

37、ction, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during

38、 S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required</p><p>　　7.1 Capture Mode</p><p>　　In the capture mode, t

39、wo options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2=1, Timer 2 performs

40、the same operation, but a 1-to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in

41、T2CON to be set. The EXF2 bit, like TF</p><p>　　7.2 Auto-reload (Up or Down Counter)</p><p>　　Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This f

42、eature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending o

43、n the value of the T2EX pin. Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2=0, Timer 2 counts up to 0FFFFH an</p><p>　　8.Baud Rate Gener

44、ator</p><p>　　Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or tr

45、ansmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 ca

46、uses the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and</p><p>　　Modes 1 and 3 Baud Rates=</p><p>　　The Timer can be configured for either timer or counter operat

47、ion. In most applications, it is configured for timer operation (CP/=0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at

48、1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.</p><p>　　Where (RCAP2H, RCAP2L) is t

49、he content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.</p><p>　　This figure is valid only if RCLK or TCLK=1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interr

50、upt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as a

51、n extra external interrupt. Note that when Timer 2 is running (TR2=1) as a timer in the baud rate generator mode, TH2 and TL2 should not be read from </p><p>　　9.Interrupts</p><p>　　The AT89S52

52、has a total of six interrupt vectors: two external interrupts ( and ), three timer interrupts (Timers 0,1 and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by

53、setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a

54、1 to this bit position, since it may be used in </p><p>　　10.Oscillator Characteristics</p><p>　　XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be con

55、figured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are no

56、requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage h</p><p>　　AT89S52單片機簡介&l

57、t;/p><p><b>　　2.引腳功能</b></p><p>　　2.1 VCC：電源</p><p>　　2.2 GND：接地</p><p>　　2.3 P0：P0口是一個8位開路漏極雙向I/O口。作為一個輸出端口，每個引腳能驅(qū)動8個TTL輸入。當對P0端口寫“1”時，引腳可被用于高阻抗輸入。當訪問外部程序和數(shù)據(jù)存

58、儲器時，P0口也可被設(shè)定低位地址/數(shù)據(jù)總線多路復(fù)用。在這種模式下，P0具有內(nèi)部上拉電阻。在Flash編程時，P0口也接收編碼字節(jié)；在程序校驗時，輸出編碼字節(jié)。程序校驗時，外部上拉電阻是必備的。</p><p>　　2.4 P1口：P1口是一個具有內(nèi)部上拉電阻的8位雙向I/O口。P1輸出緩沖器能驅(qū)動4個TTL輸入。對P1引腳寫“1”時，它們被內(nèi)部上拉電阻拉高，并且可用作輸入。用作輸入時，被外部拉低的P1引腳由于內(nèi)

59、部上拉電阻的原因，將輸出電流（IIL）。另外，P1.0和P1.1可被分別設(shè)定為定時器/計數(shù)器2的外部計數(shù)輸入（P1.0/T2）和定時器/計數(shù)器2的觸發(fā)脈沖輸入（P1.1/T2EX），如下表所示。</p><p>　　在Flash編程和校驗時，P1口也接收低位地址字節(jié)。</p><p>　　2.5 P2口：P2口是一個具有內(nèi)部上拉電阻的8位雙向I/O口。P2輸出緩沖器能驅(qū)動4個TTL輸入。對

60、P2引腳寫“1”時，它們被內(nèi)部上拉電阻拉高，并且可用作輸入。用作輸入時，被外部拉低的P2引腳由于內(nèi)部上拉電阻的原因，將輸出電流（IIL）。在訪問外部程序存儲器，以及用16位地址讀取外部數(shù)據(jù)存儲器（MOVX@DPTR）時，P2口發(fā)出高位字節(jié)。在這種應(yīng)用中，發(fā)送1時P2口使用很強的內(nèi)部上拉電阻。在使用8位地址（MOVX@RI）訪問外部數(shù)據(jù)存儲器時，P2口輸出P2特殊函數(shù)寄存器的內(nèi)容。在Flash編程和校驗時，P2口也接收高位地址字節(jié)和一些控

61、制信號。</p><p>　　2.6 P3口：P3口是一個具有內(nèi)部上拉電阻的8位雙向I/O口。P3輸出緩沖器能驅(qū)動4個TTL輸入。對P3引腳寫“1”時，它們被內(nèi)部上拉電阻拉高，并且可用作輸入。用作輸入時，被外部拉低的P3引腳由于內(nèi)部上拉電阻的原因，將輸出電流（IIL）。P3口為Flash編程和校驗接收一些控制信號。P3口也提供一些AT89S52 的特別功能，如下表所示。</p><p>　

62、　2.7 RST：復(fù)位輸入。當振蕩器重置設(shè)備時，引腳上的高電平作用2個機器工作周期?？撮T狗終止后，引腳輸出98個振蕩周期的高電平。特殊函數(shù)寄存器AUXR（地址8EH）上的DISRTO位可以使此功能無效。DISRTO默認狀態(tài)下，復(fù)位高電平功能被激活。</p><p>　　2.8 ALE/：地址鎖存器選通（ALE）是訪問外部存儲器時，鎖存低位地址的輸出脈沖。在Flash編程時，此引腳（）也用作編程脈沖輸入。在一般情況

63、下，ALE以六分之一的固定振蕩器頻率輸出，且可用來作為外部定時器或時鐘作用。然而，特別強調(diào)，在每次訪問外部數(shù)據(jù)存儲器時，ALE脈沖是跳躍的。如果需要，通過設(shè)置0位或SFR定位8EH，ALE操作將無效。經(jīng)過該位設(shè)置，ALE僅在MOVX或MOVC指令時起作用。否則，ALE將被微弱拉高。如果微控制器在外部執(zhí)行模式下，設(shè)置ALE無效位不生效。</p><p>　　2.9 ：允許程序存儲器（）是外部程序存儲器的讀選通。當A

64、T89S52從外部程序存儲器執(zhí)行代碼時，除了當每次訪問外部數(shù)據(jù)存儲器時兩個激活是跳躍的之外，在每個機器周期被激活兩次。</p><p>　　2.10 /VPP：可供外部檢查。為了使設(shè)備接收外部程序存儲器0000H至FFFFH的編碼，必須接GND。為了執(zhí)行內(nèi)部程序，應(yīng)該接VCC。在Flash編程期間，引腳也接收12伏可供編程電壓。</p><p>　　2.11 XTAL1：振蕩器反相放大器和

65、內(nèi)部時鐘發(fā)生電路的輸入端。</p><p>　　2.12 XTAL2：振蕩器反相放大器的輸出端。</p><p><b>　　3.存儲器結(jié)構(gòu)</b></p><p>　　MCS-51設(shè)備有單獨的程序和數(shù)據(jù)存儲器地址空間。每個外部程序和數(shù)據(jù)存儲器可被尋址直到64K字節(jié)。</p><p><b>　　3.1 程序存

66、儲器</b></p><p>　　如果引腳接地，所有程序都從外部存儲器取出。對于89S52，如果接VCC，地址為0000H～1FFFH的程序從內(nèi)部存儲器取出，地址為2000H～FFFFH的程序從外部存儲器取出。</p><p><b>　　3.2 數(shù)據(jù)存儲器</b></p><p>　　AT89S52有256字節(jié)片內(nèi)數(shù)據(jù)存儲器。高1

67、28字節(jié)占用與特殊功能寄存器相似的地址空間。意思是高128字節(jié)與SFR有相同的地址，而物理上不同于SFR。當一條指令訪問一個高于7FH的內(nèi)部地址時，尋址方式指定CPU訪問高128字節(jié)RAM還是SFR空間。直接尋址方式訪問特殊功能寄存器空間的說明。例如，下面的直接尋址指令訪問0A0H（P2口）的特殊功能寄存器。</p><p>　　MOV 0A0H , #data</p><p>　　使用間

68、接尋址方式訪問高128字節(jié)RAM的說明。例如，下面的間接尋址方式中，R0內(nèi)容為0A0H，訪問的是地址0A0H的數(shù)據(jù)字節(jié)，而不是P2口（它的地址也是0A0H）。</p><p>　　MOV @R0 ，#data</p><p>　　特別注意，堆棧操作也是間接尋址方式，因此高128字節(jié)數(shù)據(jù)RAM也可用于堆?？臻g。</p><p>　　4.看門狗定時器（一次性激活重置）&

69、lt;/p><p>　　WDT是一種需要軟件控制的復(fù)位方式。WDT由14位計數(shù)器和看門狗定時器復(fù)位（WDTRST）SFR構(gòu)成。WDT在重置情況下無法工作。為了使WDT工作，用戶必須往WDTRST寄存器（SFR地址為0A6H）中依次寫入01EH和0E1H。當使WDT工作后，在振蕩器運行的同時它將增加每個機器周期。WDT停止時刻依賴于外部時鐘頻率。除了復(fù)位（硬件復(fù)位或WDT溢出復(fù)位），沒有辦法停止WDT工作。當WDT溢出

70、時，它將在RST引腳驅(qū)動一個復(fù)位高脈沖輸出。</p><p><b>　　5.UART</b></p><p>　　在AT89S52中UART的操作與AT89C51和AT89C52一樣。為了獲得更深入的關(guān)于UART的信息，可點擊如下文獻鏈接：</p><p>　　http://www.atmel.com/dyn/resources/prod_d

71、ocuments/DOC4316.PDF</p><p>　　6.定時器0和定時器1</p><p>　　在AT89S52中，定時器0和定時器1的操作與AT89C51和AT89C52一樣。為了獲得更深入的關(guān)于定時器的信息，可點擊如下文獻鏈接: </p><p>　　http://www.atmel.com/dyn/resources/prod_documents/D

72、OC4316.PDF</p><p><b>　　7.定時器2</b></p><p>　　定時器2是一個16位定時器/計數(shù)器，它既可以做定時器又可以做事件計數(shù)器。其工作方式由特殊寄存器T2CON中的C/位選擇。定時器2有三種工作模式：捕捉方式、自動重載（向上或向下計數(shù)）和波特率發(fā)生器。工作模式由T2CON中的位選擇，如表6-1所示。定時器2由2個8位寄存器組成：TH

73、2和TL2。在定時工作方式中，每個機器周期TL2寄存器都會增長。由于一個機器周期由12個振蕩周期構(gòu)成，所以計數(shù)頻率就是振蕩頻率的1/12。</p><p>　　表6-1 定時器2工作模式</p><p>　　在計數(shù)工作方式下，寄存器對應(yīng)它的外部輸入引腳T2對1至0的改變作出增長的反應(yīng)。在這種方式下，每個機器周期的S5P2期間采樣外部輸入。當采樣顯示一個機器周期采樣到高電平，而下一個周期采樣

74、到低電平，計數(shù)器將增長。在檢測到跳變的這個周期的S3P1期間，新的計數(shù)值出現(xiàn)在寄存器中。因為識別1至0的跳變必須2個機器周期（24個振蕩周期），所以最大的技術(shù)頻率不高于振蕩頻率的1/24。為了確保給定的電平在改變前至少被采樣一次，電平應(yīng)該至少在一個完整的機器周期內(nèi)保持不變。</p><p><b>　　7.1捕捉方式</b></p><p>　　在捕捉模式下，通過T2

75、CON中的EXEN2來選擇兩種方式。如果EXEN2=0，定時器2是一個16位定時器或計數(shù)器，溢出時對T2CON的TF2標志置位。該位隨即引起中斷。如果EXEN2=1，定時器2執(zhí)行相同的操作，除上述作用外，在外部輸入的1至0的跳變也會使得TH2和TL2中的值分別捕捉到RCAP2H和RCAP2L中。除此之外，T2EX的跳變會引起T2CON中的EXF2置位。EXF2位像TF2一樣，會引起中斷。</p><p>　　7.

76、2自動重載（向上或向下計數(shù)）</p><p>　　當設(shè)置于16位自動重載模式下，定時器2可對其編程實現(xiàn)向上或向下計數(shù)。這一特點可以通過特殊寄存器T2MOD中的DCEN（向下計數(shù)允許）來實現(xiàn)。通過復(fù)位，DCEN被置為0，以便定時器2改為向上計數(shù)。DCEN設(shè)置后，定時器2就可以依靠T2EX引腳的值向上或向下計數(shù)。DCEN=0時，定時器2自動向上計數(shù)。該模式下，T2CON中的EXEN2位可以選擇兩種方式。如果EXEN2

77、=0，定時器2向上計數(shù)到0FFFFH后置位TF2溢出。該溢出也使得定時器寄存器重新從RCAP2H和RCAP2L中加載16位值。定時器工作于捕捉模式時，RCAP2H和RCAP2L的值可以由軟件預(yù)設(shè)。如果EXEN2=1，16位重載將被溢出和一個在外部輸入T2EX的1至0跳變其中之一觸發(fā)。這個跳變也置位EXF2。如果允許，置位TF2和EXF2都會引起中斷。如表10-2所示，置位DCEN允許定時器2向上或向下計數(shù)。在這種模式下，T2EX引腳控制

78、著計數(shù)的方向。T2EX上的一個邏輯1使得定時器2向上計數(shù)。定時器將計到0FFFFH溢出并置位TF2。該溢出也使得RCAP2H和RCAP2L中的16位值分別重載到定時器存儲器TH2和TL2中。T2</p><p><b>　　8.波特率發(fā)生器</b></p><p>　　通過設(shè)置T2CON中的TCLK和（或）RCLK可選擇定時器2作為波特率發(fā)生器。特別注意，如果定時器2

79、作為接收器或傳送器且定時器1可用于其它功能，發(fā)送和接收的波特率可以不同。設(shè)置RCLK和（或）TCLK可以使定時器2工作于波特率發(fā)生器模式。波特率發(fā)生器模式與自動重載模式相似，因此TH2的翻轉(zhuǎn)使得定時器2寄存器重載被軟件預(yù)置16位值的RCAP2H和RCAP2L中的值。模式1和模式3的波特率由定時器2按照如下溢出速率公式?jīng)Q定：</p><p>　　Modes 1 and 3 Baud Rates=</p>

80、<p>　　定時器可設(shè)置成定時器或計數(shù)器功能。在多數(shù)應(yīng)用情況下，一般配置成定時方式（CP/=0）。定時方式與用于波特率發(fā)生器的定時器2有所不同。通常，作為定時器，它在每一機器周期（1/12振蕩周期）都會增加。然而，作為波特率發(fā)生器，它在每一狀態(tài)時間（1/2振蕩周期）都會增加。波特率計算公式如下：</p><p>　　其中，（RCAP2H,RCAP2L）是RCAP2H和RCAP2L組成的16位無符號整

81、數(shù)。</p><p>　　該計算僅在T2CON中的RCLK或TCLK=1時成立。特別注意，TH2的翻轉(zhuǎn)并不置位TF2也不產(chǎn)生中斷。還需特別注意，如果EXEN2置位后，T2EX引腳上1至0跳變將置位EXF2，但不會使（RCAP2H,RCAP2L）重載到（TH2，TL2）中。因此，當定時器2作為波特率發(fā)生器時，T2EX也還可以作為一個額外的外部中斷。特別注意，當定時器2處于波特率發(fā)生器模式作為定時器時（TR2=1），

82、TH2和TL2不應(yīng)該被讀或?qū)?。在這種模式下，定時器在每一狀態(tài)都會增加，讀或?qū)懙慕Y(jié)果就不會準確。寄存器RCAP2可以讀但不能寫，因為寫可能和重載重疊，并造成寫和（或）重載錯誤。在訪問定時器2或RCAP2寄存器前，定時器應(yīng)該被關(guān)閉（TR2清0）。</p><p><b>　　9.中斷</b></p><p>　　AT89S52總共有6個中斷源：兩個外部中斷（和），三個定時

83、中斷（定時器0、1、2）和一個串行端口中斷。每個中斷源都可以通過置位或清除特殊寄存器IE中的位分別使其有效或無效。IE還包括一個總無效位EA，它能一次使所有中斷無效。特別注意，IE.6位是未生效的。用戶軟件不應(yīng)給這些位寫1，因為它們?yōu)锳T89系列新產(chǎn)品預(yù)留。定時器2的中斷可以被寄存器T2CON中的TF2和EXF2的或邏輯觸發(fā)。當服務(wù)程序啟動后，這些標志位都可以由硬件清0。實際上，中斷服務(wù)程序必須判定是否是TF2或EXF2激活中斷，標志位

84、也必須由軟件清0。定時器0和定時器1的標志位TF0和TF1，在計數(shù)溢出的那個周期的S5P2被置位。它們的值隨即在下一個周期被電路捕捉。然而，定時器2的標志位TF2在S2P2被置位，在同一個定時器溢出周期被電路捕捉下來。</p><p><b>　　10.振蕩器特性</b></p><p>　　XTAL1和XTAL2分別是一種作為單片的振蕩器的反相放大器的輸入、輸出端。