外文翻譯---觸發(fā)器

1、<p><b>　　英文資料及中文翻譯</b></p><p>　　FLIP-FLOPS</p><p>　　1 Intorduce</p><p>　　In this passage, we show how to design flip-flops, which operate as one-bit memory cells. F

2、lip-flops are also called latches. Logic circuits constructed using flip-flops can have the present output be a function of both the past and present inputs. Such circuits are called senfiential logic circuits.</p>

3、<p>　　All flip-flops are based on the same principle: Positive feedback is used to produce a circuit that is bistable . A bistable circuit is one that has two stable operating points. Which operating point the cir

4、cuit is in is called the state of the circuit. If the state can be sensed and changed, then the circuit can function as a one-bit memory element.</p><p>　　The simplest bistable circuit is constructed using t

5、wo inverters in a loop as shown in Figure 1－1.This circuit only has two nodes, A and B. Because of the inverters, if A is high, B must be low and vice versa; hence, the circuit has two stable states.</p><p>

6、　　The operation of the bistable circuit can also be viewed using a plot of the transfer characteristic of the two inverters in series, as shown in Figure 1－2. Part (a) of the figure shows the static transfer characterist

7、ic of one of the inverters. When the input voltage is below the threshold (a logical ZERO), the output voltage is high (a logical ONE). When the input voltage is greater than the threshold, the output voltage is low. In

8、part (b) of the figure, we show the transfer characteristic th</p><p>　　The point where the load line intersects the middle of the transfer characteristic is not stable. To see that this statement is true, s

9、uppose for the moment that the circuit is at this point. If the input voltage increases at all (due to noise or some change in the circuit), the output voltage of the inverters must also increase. But the output is input

10、, so as it increases, it causes further increases in the output, and the original change is magnified. This positive feedback will quickly drive </p><p>　　In the sections that follow, we show how we can move

11、 this bistable circuit from one operating point to the other. The internal positive feedback will then hold the circuit at that state until we deliberately change it; hence, the circuit has memory.</p><p>　　

12、Figure 1－1A bistable circuit</p><p><b>　　(a)</b></p><p><b>　　(b)</b></p><p>　　Figure 1－2 (a) One inverter and its transfer characteristic </p><p&g

13、t;　　(b) The transfer characteristic for two inverters in series and the load line for the circuit </p><p>　　2 The Set-Reset Flip-Flop</p><p>　　A set-reset (SR) flip-flop is shown in Figure 2－1(a

14、). A table describing the function of the circuit is shown in part (b) of the figure, and the schematic symbol is shown in part (c). This function table is similar to a truth table, but it describes a dynamic situation,

15、not a static one. The output is the output at some discrete time, denoted by Qn, and the table includes an entry for the previous state of the flip-flop (Qn-1). Although the circuit is drawn differently, the two NOR gate

16、s are in </p><p><b>　　(a)</b></p><p><b>　?。╞）</b></p><p><b>　　(c)</b></p><p>　　Figure 2－1 (a) An SR flip-flop, </p><p>

17、;　　(b) a table describing the circuits function</p><p>　　(c) the schematic symbol.</p><p>　　The circuit operates in the following way: If both inputs (S and R) are zero, the previous state is re

18、tained. Suppose, for example, that Qn-1 is high (i.e., ONE). Then the output of the bottom NOR, which isn-1 , will be low (i.e., ZERO), independently of what S is. In this case, both inputs to the top NOR are low, so its

19、 output is high, as originally assumed. Now suppose that Qn-1 is low. In this case, both inputs to the bottom NOR are low, so n-1 is high. Therefore, the output of the top NOR, Q</p><p>　　Now consider what h

20、appens when the set input, S, goes high while R remains low. The output of the bottom NOR, n-1 , will now go low, independent of what the previous state of the circuit was. With R low as well, this guarantees that Qn wil

21、l go high (i.e, the flip-flop has been “set”). Note that S does not have to stay high. Once the flip-flop is set, the S input can go low again, and the state will be retained. This sequence of events is illustrated in Fi

22、gure 2－2 The figure shows that there is s</p><p>　　Figure 2－2 A timing diagram for the SR flip-flop. The arrows indicate which transition causes the following change.</p><p>　　The operation of t

23、he reset input is similar. If R goes high while S is kept low, the output of the top NOR, Qn, will go low (i.e., the flip-flop is “reset”). With Qn and S both low, the bottom NOR output will be high. The reset input can

24、go low again, and this new state will be retained. This sequence is also illustrated in Figure 2－2.</p><p>　　Finally, we note that both inputs should not be allowed to go high at the same time. If this happe

25、ns, both NOR outputs go low, so Q and are not complements anymore. Also, if both inputs are high and then go low at exactly the same time, we can’t predict what the resulting output state will be, since both outputs wil

26、l try to go high, which is a condition that cannot be sustained. Which output will actually stay high depends on mismatches in the NOR gates and cannot be predicted.</p><p>　　3 The JK Flip-Flop</p>&l

27、t;p>　　The fact that the output of an SR flip-flop is undefined if both inputs go high is troublesome in many applications. The JK flip-flop avoids this problem and is more flexible in its operation. The JK flip-flop i

28、s a clocked flip-flop; that is, it requires a separate clock input to operate. This clock signal is usually a square wave with a fixed period. Logic circuits that require a clock and that only allow output transitions to

29、 occur in synchrony with the clock are called synchronous-logic circu</p><p><b>　　(a)</b></p><p><b>　　(b)</b></p><p><b>　　(c) </b></p><

30、;p>　　Figure 3－1 (a) A JK flip-flop made using an SR flip-flop. (b) The Schematic symbol for a JK flip-flop (c) the function table. (The flip-flop only changes state when the clock is high.)</p><p>　　A JK

31、flip-flop is shown in Figure 3－1(a); the schematic symbol is shown in part (b) of the figure, and the function table is shown in part (c). The AND gates serve to enable the inputs to the SR flip-flop. That is, only when

32、the clock is high are the J and K inputs able to affect the SR flip-flop. In addition to needing the clock to be high, the J input affects S only if the SR flip-flop is currently reset, and the K input affects R only if

33、the flip-flop is currently set. Therefore, we see that </p><p>　　The JK flip-flop as shown in Figure 3－1has a major problem: It will work only if the clock pulse width (i.e., the time the clock is high) is s

34、hort compared with the propagation delay of the gate. To understand this limitation, consider what happens when J and K are both high and Qn-1 is low. In this case, the output of the flip-flop will toggle when the clock

35、goes high, as indicated in the function table. But, if the output toggles and the clock is still high, the output will toggle again . This</p><p>　　A master-slave JK flip-flop is shown in Figure 3－2. The mas

36、ter flip-flop is enabled when the clock is high, so the data are latched into the master during that portion of the clock cycle. During that time, c is low and the slave is disabled and holds the previous value. Then the

37、 clock goes low, c goes high and enables the slave. The data from the master are then transferred to the slave and show up at the output. Since the master and slave flip-flops are never enabled at the same time, the outp

38、u</p><p>　　Figure 3－2 A master-slave JK flip-flop</p><p>　　In designing a master-slave JK flip-flop, we must carefully consider the propagation delays of the individual gates to prevent the slav

39、e from changing before it should. For example, in the figure, the data on SM and RM can change one gate delay after the clock goes high. The slave clock, which is c, goes low one inverter delay after the clock goes high.

40、 We must be sure that the slave clock changes before the output of the master flip-flop can change; otherwise, the data will pass on through to t</p><p>　　The JK flip-flop just described is level-triggered f

41、lip-flop; that is, the master is enabled when the clock level is high, and the slave is enabled when the clock level is low. The problem with level-triggered JK flip-flops is that they are sensitive to glitches on the in

42、puts at certain points in the operation. For example, suppose that the previous state of the flip-flop was Q=0 and that we are now ready for the next clock cycle. Suppose further that J=0 and K=1, so we are resetting the

43、 flip-fl</p><p>　　An edge-triggered JK flip-flop is shown in Figure 3－3(a), and the schematic symbol is shown in part (b) of the figure. The triangle inside the block in part (b) indicates that the flip-flop

44、 is edge-triggered. as explained in a moment, and the bubble indicates that it is negative edge triggered (i.e., the input is latched on the negative-going edge of the clock ).</p><p>　　(a)

45、 (b)</p><p>　　Figure 3－3 (a) An edge-triggered JK flip-flop (b) the schematic symbol for it </p><p>　　To understand how this circuit operates, we need to first examine the input ga

46、te structure. Consider, for example, the situation where Q=0 and we want to set the flip-flop, so J=1. Part of the input structure is shown in Figure 3－4(a) for this case, and the corresponding waveforms are shown in par

47、t (b) of the figure.</p><p>　　(a) (b)</p><p>　　Figure 3－4(a) A part of the input circuit when Q=0. </p><p>　　(b) The resulting waveforms.&l

48、t;/p><p>　　The bubbles at the input of the second gate invert the inputs so that the AND is true when both inputs are low. Because Q=0, we know that =1. Now, with J=1, the output of the NAND gate, Jc, will be t

49、he inverse of the clock, delayed by one gate delay. Therefore, when the clock goes low, Jc will go high one gate delay later, as shown. During that gate delay, both inputs to the second gate are low, so the AND is true a

50、nd S goes high. In other words, the negative edge of the clock has produced a nar</p><p>　　4 The D Flip-Flop</p><p>　　A D flip-flop is shown is Figure 4－1(a), and its schematic symbol is shown i

51、n part (b) of the figure. This flip-flop implements a digital delay; that is, the output at the end of each clock cycle is equal to the input on the previous cycle, as seen in the function table in part (c) of the figure

52、－h(huán)ence the name D flip-flop. This particular circuit is positive-edge triggered, so the output changes state slightly after the positive-going edge of the clock. The output is insensitive to the value of </p><

53、p><b>　　(a)</b></p><p><b>　　(b)</b></p><p><b>　　(c) </b></p><p>　　Figure 4－1 (a) A D flip-flop (b) its schematic symbol (c) the function table.

54、 </p><p>　　Clocked flip-flops also frequently have asynchronous clear and preset inputs, as shown for a D flop-flop in Figure 4－2. The preset input will set the flip-flop so that Q=1 at any time, regardless

55、of the state of the clock; that is what is meant by being asynchronous. In similar fashion, the clear input will clear the flip-flop so that Q=0 at any time.</p><p>　　Figure 4－2 A D flip-flop with preset and

56、 clear inputs </p><p><b>　　觸發(fā)器</b></p><p><b>　　1簡(jiǎn)介</b></p><p>　　本文，我們將介紹如何設(shè)計(jì)可作為一位存儲(chǔ)單元的觸發(fā)器。觸發(fā)器也可稱為鎖存器。采用觸發(fā)器的邏輯電路結(jié)構(gòu)其當(dāng)前的輸出是電路的前一穩(wěn)定狀態(tài)和當(dāng)前穩(wěn)定狀態(tài)的函數(shù)。這樣的電路稱為時(shí)序邏輯電路。<

57、;/p><p>　　所有的觸發(fā)器都遵循同一規(guī)則：正反饋用來(lái)生成雙穩(wěn)態(tài)電路，雙穩(wěn)態(tài)電路是一個(gè)具有兩個(gè)穩(wěn)定工作點(diǎn)的電路。電路所處的工作點(diǎn)稱為電路的一個(gè)狀態(tài)。如果其狀態(tài)能夠讀出和改變，那么此電路就可以作為一個(gè)一位存儲(chǔ)器單元。</p><p>　　最簡(jiǎn)單的雙穩(wěn)態(tài)電路是在一個(gè)回路中利用兩個(gè)反相器構(gòu)成的。如圖1－1所示。這個(gè)電路只有兩個(gè)節(jié)點(diǎn)，A和B。由于是反相器，所以如果A是高電平,那么B就必須是低電平，

58、或者反相。因此，電路具有兩個(gè)穩(wěn)定狀態(tài)。</p><p>　　也可以通過(guò)兩個(gè)串聯(lián)的反相器的傳輸特性曲線圖來(lái)查看雙穩(wěn)態(tài)電路的操作，如圖1－2所示。突1－2（a）給出了其中一個(gè)反相器的靜態(tài)傳輸特性。當(dāng)輸入電壓低于門(mén)限電壓（邏輯0），輸出電壓變?yōu)楦唠娖剑ㄟ壿?）。當(dāng)輸入電壓超過(guò)門(mén)限電壓，則輸出為低電平。在圖1－2（b），給出了將兩個(gè)反相器串聯(lián)后所得到的傳輸特性曲線。該電路邏輯等式的任何一個(gè)結(jié)果都必須落在這條特性曲線上。由

59、于是外部連接，兩個(gè)反相器的串聯(lián)連接處的輸入輸出電壓必須相等。因此，再在圖中劃出一條單位斜率的直線。這條線稱為負(fù)載線，因?yàn)樗砹藘蓚€(gè)串聯(lián)反相器的外部負(fù)載的關(guān)系。該電路邏輯等式的任何一個(gè)解也必須落在負(fù)載線上。因此，如果將這兩個(gè)等式聯(lián)立求解，就可以得到唯一的工作點(diǎn)，這一點(diǎn)正是負(fù)載直線與傳輸特性曲線的交點(diǎn)。在圖中的曲線上一共有三個(gè)交點(diǎn)，但是只有其中兩個(gè)是穩(wěn)定的，正如我們將要論證的。</p><p>　　圖 1－1雙穩(wěn)態(tài)

60、電路</p><p><b>　　(a)</b></p><p><b>　　（b）</b></p><p>　　圖 1－2（a）反相器和它的傳輸特性 </p><p>　?。╞）兩個(gè)反相器串聯(lián)的傳輸特性和負(fù)載曲線</p><p>　　負(fù)載直線與傳輸特性曲線中部的交點(diǎn)是不穩(wěn)定

61、的。為了證明這點(diǎn)，假設(shè)在某一時(shí)刻電路工作與這一點(diǎn)。如果無(wú)論何時(shí)輸入電壓增加了（由于噪聲或是電路發(fā)生一些變化），反相器的輸出電壓也必須增大。但是由于輸出就是輸入，因此它的增大會(huì)導(dǎo)致輸出的進(jìn)一步增加，原有的變化被放大了。這樣的正反饋將迅速驅(qū)動(dòng)電路達(dá)到所示的頂端的工作點(diǎn)。在那一點(diǎn)，二反相器鏈的輸入輸出電壓都很高，而中間點(diǎn)電壓（圖1－1中的vB）較低。因此電路是穩(wěn)定的并且能夠永遠(yuǎn)保持著狀態(tài)。如果從中間點(diǎn)開(kāi)始讓輸入電壓減小一點(diǎn)，那么會(huì)落在更低的工

62、作點(diǎn)上，再次達(dá)到穩(wěn)定。</p><p>　　在接下來(lái)的部分，我們將說(shuō)明如何使這個(gè)雙穩(wěn)態(tài)電路從一個(gè)工作狀態(tài)轉(zhuǎn)移到另一個(gè)工作狀態(tài)，但是，內(nèi)部的正反饋將會(huì)使電路保持在這個(gè)狀態(tài)直到有意改變它。因此電路具有記憶。</p><p><b>　　2 SR觸發(fā)器</b></p><p>　　SR（設(shè)置-復(fù)位）觸發(fā)器如圖2－1（a）所示。圖2－1（b）給出了電路

63、的功能表，而圖2－1(c)給出了它的電路邏輯符號(hào)。這個(gè)功能表與真值表類似，但它描述的是動(dòng)態(tài)的情況，而不是靜態(tài)的。其輸出是在一些離散時(shí)間上的輸出，用Qn表示，此外表中還包括觸發(fā)器前一狀態(tài)的輸入(Qn-1)。雖然所畫(huà)的電路與上節(jié)所講得不相同，但它也是兩個(gè)或非門(mén)串聯(lián)在一起，就像圖1－2(b)中的兩個(gè)反相器一樣。這里所示的結(jié)構(gòu)通常也被描述為交叉耦合。觸發(fā)器的兩個(gè)輸出是互補(bǔ)的。我們通常認(rèn)為輸出Q是觸發(fā)器的狀態(tài)。</p><p&

64、gt;<b>　　(a)</b></p><p><b>　?。╞）</b></p><p><b>　　(c) </b></p><p>　　圖 2－1 (a) SR觸發(fā)器 （b）描述電路的功能表 （c）電路邏輯符號(hào)</p><p>　　該電路的工作原理如下：如果兩個(gè)輸入端(

65、S和R)都是邏輯0，則保持前一狀態(tài)。例如，假設(shè)Qn-1時(shí)高電平（即邏輯1），那么無(wú)論S是什么狀態(tài)，下面那個(gè)或非門(mén)的輸出 n-1 都將是低電平(即邏輯0)。在這種情況下，上面那個(gè)或非門(mén)的兩個(gè)輸入端都是低電平，因此它的輸出是高電平，正如前面所假設(shè)的那樣?，F(xiàn)在，我們假設(shè)Qn-1是低電平。在這種情況下，下面那個(gè)或非門(mén)的兩個(gè)輸入都是低電平，所以其輸出 n-1 為高電平。因此，上面那個(gè)或非門(mén)的輸出Qn-1就像假設(shè)的那樣是低電平。</p&g

66、t;<p>　　現(xiàn)在考慮當(dāng)置1端S為高電平而置0端R保持低電平時(shí)會(huì)發(fā)生什么情況。這時(shí)無(wú)論電路的前一狀態(tài)是怎樣的，下方的或非門(mén)的輸出 n-1 都將變?yōu)榈碗娖?。再加上R也是低電平，這就保證了Qn將變?yōu)楦唠娖剑从|發(fā)器被置位為1）。注意，S不必一直處于高電平，一旦觸發(fā)器被置1，輸入端S便可再次回到低電平，狀態(tài)將被保持。整個(gè)過(guò)程的順序在圖2－2中用圖解進(jìn)行了說(shuō)明。從圖中可以看到，在通過(guò)每一個(gè)門(mén)時(shí)都有一定的延時(shí)。因此，在門(mén)輸入端的變

67、化需要延遲一個(gè)時(shí)間td才能影響到輸出端。</p><p>　　圖2－2 SR 觸發(fā)器的時(shí)序圖 箭頭表明此處輸入電平的轉(zhuǎn)換引起的隨后輸出的變化</p><p>　　置0輸入端的工作原理是類似的。如果R達(dá)到高電平而S保持而低電平，那么上面那個(gè)或非門(mén)的輸出Qn將變?yōu)榈碗娖剑从|發(fā)器被置0）。由于Qn和S都為低電平，下方的或非門(mén)的輸出將為高電平。此時(shí)置0端可以再次回到低電平，新的狀態(tài)將被保持。其順

68、序在圖2—2中也有圖解說(shuō)明。</p><p>　　最后，要注意這兩個(gè)輸入端不允許同時(shí)為高電平。如果發(fā)生這種情況，兩個(gè)或非門(mén)的輸出都為低電平，而Q和 也不再互補(bǔ)。同樣，如果兩個(gè)輸入端同時(shí)為高電平又在同一時(shí)刻變?yōu)榈碗娖?，那么我們將不能預(yù)測(cè)輸出結(jié)果會(huì)是什么狀態(tài)，這是因?yàn)閮蓚€(gè)輸出端都將試圖變?yōu)楦唠娖?，而這種情況是不可維持的。如果輸出狀態(tài)真都保持在高電平，則主要是由或非門(mén)失陪引起的。</p><p>

69、;<b>　　3 JK觸發(fā)器</b></p><p>　　事實(shí)上，當(dāng)兩個(gè)輸入端都是高電平時(shí)，SR觸發(fā)器的輸出沒(méi)有定義，這在許多應(yīng)用中很不方便。JK觸發(fā)器就避免了這個(gè)問(wèn)題，在應(yīng)用中更加靈活。JK觸發(fā)器是一個(gè)時(shí)鐘觸發(fā)器，也就是說(shuō)，它需要一個(gè)單獨(dú)的時(shí)鐘輸入端口進(jìn)行驅(qū)動(dòng)。這個(gè)時(shí)鐘信號(hào)通常是具有固定周期的方波。需要一個(gè)時(shí)鐘信號(hào)并且其輸出的轉(zhuǎn)變必須和這個(gè)時(shí)鐘信號(hào)同步，這樣的邏輯電路稱之為同步邏輯電路。時(shí)

70、鐘信號(hào)可以用一個(gè)非穩(wěn)態(tài)的多頻振蕩器來(lái)產(chǎn)生，正如前所述。</p><p>　　JK觸發(fā)器如圖3－1(a)所示，其電路邏輯符號(hào)和功能表分別如圖3－1(b)和圖3－1(c)所示。與門(mén)用于啟動(dòng)SR觸發(fā)器的輸入端。這意味著只有當(dāng)時(shí)鐘信號(hào)為高電平時(shí)，J和K這兩個(gè)輸入才能影響SR觸發(fā)器。除了要求時(shí)鐘信號(hào)為高電平之外，只有當(dāng)SR觸發(fā)器當(dāng)前被置0時(shí)，J輸入才能影響到S，或者只有當(dāng)SK觸發(fā)器當(dāng)前被置1時(shí)，K輸入才能影響到R。因此，我

71、們注意到當(dāng)J和K都為低電平時(shí)，S和R也都為低電平，而觸發(fā)器會(huì)保持目前的狀態(tài)，和SR觸發(fā)器一樣。當(dāng)J是高電平而這時(shí)觸發(fā)器被置1(即 n-1 為高電平)，那么當(dāng)時(shí)鐘信號(hào)達(dá)到高電平時(shí)，無(wú)論K處于什么狀態(tài)觸發(fā)器都將會(huì)被置0。如果K是高電平而這時(shí)觸發(fā)器被置0（即Qn-1為高電平），那么當(dāng)時(shí)鐘信號(hào)達(dá)到高電平時(shí)，無(wú)論J處于什么狀態(tài)觸發(fā)器都將會(huì)被置1。接著如果J和K都為高電平，在時(shí)鐘信號(hào)達(dá)到高電平時(shí)觸發(fā)器將翻轉(zhuǎn)。工作與翻轉(zhuǎn)模式下得JK觸發(fā)器有時(shí)也叫做T

72、觸發(fā)器。</p><p><b>　　(a)</b></p><p><b>　　(b)</b></p><p><b>　　(c) </b></p><p>　　圖 3－1 （a）用SR觸發(fā)器組成的JK觸發(fā)器 （b）JK觸發(fā)器的電路邏輯符號(hào)</p><p&

73、gt;　?。╟）功能表（只有當(dāng)時(shí)鐘信號(hào)處于高電平時(shí)觸發(fā)器才能改變狀態(tài)）</p><p>　　圖3－1中示出的JK觸發(fā)器有一個(gè)較大的問(wèn)題：只有當(dāng)時(shí)鐘脈沖寬度（即時(shí)鐘信號(hào)處于高電平的時(shí)間）與門(mén)級(jí)延時(shí)時(shí)間相比很小時(shí)，觸發(fā)器才能工作。為了理解這一局限性，考慮當(dāng)J和K都為高電平而Qn-1位低電平時(shí)會(huì)發(fā)生什么情況。在這種情況下，當(dāng)時(shí)鐘信號(hào)達(dá)到高電平時(shí)觸發(fā)器的輸出將會(huì)發(fā)生翻轉(zhuǎn)，正如功能表中說(shuō)明的那樣。但是，如果輸出翻轉(zhuǎn)后時(shí)鐘信

74、號(hào)仍保持為高電平，輸出將會(huì)再次翻轉(zhuǎn)。這個(gè)過(guò)程將會(huì)不斷重復(fù)，直到時(shí)鐘信號(hào)回到低電平或者使J或K改變。為了避免這種情況，我們使用主從式JK觸發(fā)器。</p><p>　　在圖3－2中給出了一個(gè)主從式JK觸發(fā)器。由于主觸發(fā)器只有在時(shí)鐘信號(hào)為高電平時(shí)才被啟動(dòng)，因此在時(shí)鐘周期的這一部分?jǐn)?shù)據(jù)被鎖存在主觸發(fā)器中。在這段時(shí)間內(nèi)，C 是低電平，從觸發(fā)器被禁止，保持前一狀態(tài)的值。然后，時(shí)鐘信號(hào)回到低電平，C變?yōu)楦唠娖絾?dòng)從觸發(fā)器。這時(shí)

75、數(shù)據(jù)將有主觸發(fā)器傳給從觸發(fā)器，最后出現(xiàn)在輸出端。由于主觸發(fā)器和從觸發(fā)器絕對(duì)不會(huì)被同時(shí)啟動(dòng)，所以即使時(shí)鐘信號(hào)在任何一個(gè)狀態(tài)保持太長(zhǎng)的時(shí)間，輸出也不會(huì)繼續(xù)翻轉(zhuǎn)。時(shí)鐘信號(hào)必須在每一狀態(tài)局持續(xù)足夠長(zhǎng)的時(shí)間，以保證滿足人以一個(gè)門(mén)的傳輸延時(shí)要求。</p><p>　　在設(shè)計(jì)主從式JK觸發(fā)器時(shí)，我們必須仔細(xì)地考慮各個(gè)門(mén)的傳輸延時(shí)以防止從觸發(fā)器提前變化。比如在圖中，SM和RM端的數(shù)據(jù)可能在時(shí)鐘信號(hào)達(dá)到高電平后延遲一個(gè)門(mén)級(jí)延時(shí)才變

76、化。同樣從觸發(fā)器的時(shí)鐘信號(hào) 將在時(shí)鐘信號(hào)變?yōu)楦唠娖胶笱舆t一個(gè)反相器的門(mén)級(jí)延時(shí)才變?yōu)榈碗娖健Ｎ覀儽仨毐ＷC在主觸發(fā)器的輸出改變之前從觸發(fā)器的是中就發(fā)生變化；否則，數(shù)據(jù)將直接通過(guò)主觸發(fā)器傳送給從觸發(fā)器，而不能實(shí)現(xiàn)我們的初衷。同樣，當(dāng)時(shí)鐘信號(hào)回到低電平，也必須保證在從觸發(fā)器的輸出改變之前主觸發(fā)器已經(jīng)被禁止。</p><p>　　圖3－2主從式JK觸發(fā)器</p><p>　　上述的JK觸發(fā)器是電平

77、觸發(fā)式觸發(fā)器，也就是說(shuō)，當(dāng)時(shí)鐘信號(hào)為高電平時(shí)啟動(dòng)主觸發(fā)器，而在時(shí)鐘信號(hào)為低電平時(shí)啟動(dòng)從觸發(fā)器。電平觸發(fā)式JK觸發(fā)器的問(wèn)題是在某些條件下觸發(fā)器對(duì)輸入端的尖脈沖信號(hào)非常敏感。例如，假設(shè)觸發(fā)器的前一狀態(tài)是Q=0而且已經(jīng)為下一個(gè)時(shí)鐘周期做好準(zhǔn)備，進(jìn)一步假設(shè)J=0,K=1,所以再次將觸發(fā)器復(fù)位。換句話說(shuō)，不希望觸發(fā)器的狀態(tài)發(fā)生改變。在這種情況下，但是時(shí)鐘信號(hào)為高電平時(shí)，SM 和 RM均為低電平，因此主觸發(fā)器的輸出不會(huì)發(fā)生變化。然而，如果在時(shí)鐘信號(hào)

78、回到低電平之前在J輸入端出現(xiàn)一個(gè)正的尖脈沖信號(hào)，他將被傳遞到SM端，將主觸發(fā)器置位。由于Q為低電平，驅(qū)動(dòng)RM的與門(mén)被禁止，所以不可能將觸發(fā)器復(fù)位。結(jié)果，當(dāng)時(shí)鐘信號(hào)回到低電平時(shí)，這個(gè)錯(cuò)誤將會(huì)傳給從觸發(fā)器。</p><p>　　圖3－3（a）中給出了一個(gè)邊沿觸發(fā)的JK觸發(fā)器，其電路邏輯符號(hào)如圖3—3(b)所示。圖3－3(b)的符號(hào)中的三角形表示觸發(fā)器時(shí)邊沿觸發(fā)的，就是在一瞬間觸發(fā)；模塊內(nèi)的圓圈表示觸發(fā)器是負(fù)邊沿觸發(fā)（

79、即在時(shí)鐘的下跳沿輸入被鎖存）</p><p><b>　　（a）</b></p><p><b>　?。╞）</b></p><p>　　圖 3－3（a）邊沿觸發(fā)的JK觸發(fā)器 （b）其電路邏輯符號(hào)</p><p>　　要理解這個(gè)電路的工作原理，首先需要檢驗(yàn)輸入們的結(jié)構(gòu)。例如，考慮災(zāi)Q=0的情況下，想

80、要將觸發(fā)器置位，所以要求J=1。這種情況下的部分輸入電路結(jié)構(gòu)如3－4(a)所示，圖3－4(b)給出了其相應(yīng)的波形。</p><p><b>　　（a）</b></p><p><b>　?。╞）</b></p><p>　　圖 3－4（a）Q=0時(shí)的部分輸入電路（b）結(jié)果波形</p><p>　　在

81、第二個(gè)門(mén)的輸入端的圓圈將輸入信號(hào)反相，所以當(dāng)兩個(gè)輸入端都為低電平時(shí)與門(mén)被打開(kāi)。由于Q=0，所以我們知道 =1。此刻，由于J=1，所以與門(mén)的輸出Jc是時(shí)鐘信號(hào)的反相且延遲一個(gè)門(mén)級(jí)延時(shí)。因此，當(dāng)時(shí)鐘信號(hào)回到低電平時(shí)，與門(mén)的輸出Jc在一個(gè)門(mén)級(jí)延時(shí)后將變?yōu)楦唠娖?。在門(mén)級(jí)延時(shí)是期間，第二個(gè)門(mén)的兩個(gè)輸入端都是低電平，則與門(mén)輸出高電平，S變?yōu)楦唠娖健?高電平，時(shí)鐘的下降沿在S端產(chǎn)生了一個(gè)窄脈沖。同樣，如果K輸入為高電平而

82、Q=1，那么時(shí)鐘的下降沿將會(huì)在R端上產(chǎn)生一個(gè)窄脈沖。這樣，只有在時(shí)鐘的下降沿SR觸發(fā)器才會(huì)被置1或置0。只要在時(shí)鐘沿到來(lái)之前，J和K輸入保持一個(gè)很短的時(shí)間不變（稱為建立時(shí)間），而且在時(shí)鐘沿到來(lái)之后保持一個(gè)很短的時(shí)間不變（稱為保持時(shí)間），那么電路對(duì)輸入端的尖峰信號(hào)就不敏感了。我們也可以制作上跳沿觸發(fā)電路。</p><p><b>　　4 D觸發(fā)器</b></p><p>

83、;　　D觸發(fā)器如圖4－1(a)所示，其電路邏輯符號(hào)如圖4－1(b)所示。該觸發(fā)器可實(shí)現(xiàn)一個(gè)數(shù)字延時(shí)，如同我們從圖4－1(c)給出的函數(shù)功能表中所看到的，在每一個(gè)時(shí)鐘周期的末端，其輸出等與前一周期的輸入，因此將其命名為D觸發(fā)器。這個(gè)特殊的電路是上升沿觸發(fā)，因此其輸出在時(shí)鐘的上升沿之后立刻改變其狀態(tài)。除了在時(shí)鐘上升沿之前（建立時(shí)間）和之后（保持時(shí)間）的一個(gè)很短的時(shí)間內(nèi)，輸出端對(duì)D輸入端的數(shù)據(jù)都不敏感。D觸發(fā)器在移位寄存器和計(jì)數(shù)器中有著廣泛的

84、應(yīng)用。 </p><p>　　鐘控觸發(fā)器也常常帶有異步清零和置位端，如圖4—2所示的D觸發(fā)器。置位端將觸發(fā)器置位為1，所以無(wú)論時(shí)鐘處于何種狀態(tài)，任何時(shí)候都有Q=1；這就是所謂的異步。同樣，清零端將會(huì)把觸發(fā)器置位為0，因此任何時(shí)候都有Q=0。</p><p>　　無(wú)論時(shí)鐘處于什么狀態(tài)，置位端在任何時(shí)間均可將觸發(fā)器置位為1，即所謂的異步置位。同樣，清零端在任何時(shí)間均可將觸發(fā)器置位為0。<

85、/p><p><b>　　（a）</b></p><p><b>　　(b)</b></p><p><b>　　( c) </b></p><p>　　圖4－1 （a）D觸發(fā)器 （b）其電路邏輯符號(hào) （c）函數(shù)功能表</p><p>　　圖4－2 帶有置位