外文翻譯--基于dsp的實時圖像處理系統(tǒng)的設(shè)計平臺（英文）

1、A DSP-Based Platform for Rapid Prototyping of Real Time I mage Processing Systems. V. Gemignani, F. Faita, M. Giannoni, A. Benassi CNR, instilute qfClinical Physio/ORY, Pisa, ITALY gemi@(fc.cnr. it Abstract 7his paper

2、jil'esents an embedded board jiJl“ rapid prof{)?vpiJIR of reul time image processing o/gorithms. The p/a(/iJl“!l1 is hosed {)/1 tlte Texas l/1s/ruments' TMS320C6415, a new dir,i/al siKllal processor designed .

3、/iN' h(gh pel/i)/'manee applications. Any ana/oK video source, slIeh os a camcorder or (/ VCR. can he used as un illput signal. The images arc captured, processed in rea/ time and then displayed in {/ window o/a

4、R/“{/phiml lIser inlel/hee. Both {/ mouse and {/ keyhoard are avai/ahle 10 interae/ with the s yslem. A sojiware environment is a/so proVided thus allowinK the rapid implementation (?/ the algori/hms in high-lev

5、el lanRuage. This work was partially Slipported by Esoate S.p.A. .- Flon:nce, !TAL Y. 1. Introduction The implementation of real time imaging algorithms is a challenging task. When dealing with olnine applications, stan

6、dard workstations arc commonly llsed, wherc pOWerf ul soHware tools arc availahle, thanks to which image-processing procedures can be easily dc:vc:loped. The algorithms are implemented in high level language and a f

7、lexible graphical lIscr interl?lce (GUI) can be used to interact with the system and to displilY the results. Moreover, such systems maintain their compatibility with older vel'sions, so the soJlwarc can be easily r

8、e-implemented as soon as a new, faster platform is available. Un[ertunately, a solution based 011 a standard workstation is oilcn unsuitable for real timc imaging [11. In reecnt years, several special hardware platforms

9、have been developed to meet the requirements of real­time imaging. l-l ighly customized systems require the design of (he architecture at the integrated circuit (lC) level l2J. In general, such solutions provide th

10、e best perllJrmances but have two drawbacks: (i) their I[lck or Ilexihility as the ICg arc designed to perform only speeilic elaborations; (ii) their elevated design cost and long time-to-market which limit slLch an appr

11、oach oilly to critical applications and to mass production. Morc affordable lind more Ilexible solutions arc based 011 programmable devices, mainly Digital Signal Processors (DSPs) [lnd Field Programmable nate A

12、rrays (FI'GAs) [3,4,5]. The perlennance/cost ratio Ihr such devices has rapidly increased so they arc becoming a valid altcrnative [0 Ie level design. Moreover, they allow the development 01' general

13、3;purpose programmable platform8, which can be adopted by sollwarc developers to implement custom algorithms. SUl:h solutions arc witldy lIsed when rapid prototyping is required. A common objection to the lise

14、 of ClistOIll pmgral111l1ablc platforms is that implementing algorithms may be din1cult as speeilie knowledge of the hardware in lise is necessary. Systems based on programmable logics, sLleh as FPGA, mllst be

15、programmed ill a hardware description Iangllag? (IIDL). The approach is quite different from the soHware solution lIsed in workstations as it covers aspects 01“ hardware design. In systems based 011 microproces

16、sors, such as IJSPs, the task is slightly easier sinee it is still based on a sort ware approach. Furthermore, modern eotnpi lers allow a high level language to be used to obtain optimized code implcmentations, c

17、ven though, when till.: highest level of optimization is required, the algorithm must still be written in hand-cockd Assembler so the work hecomes far Illore difficult. Nonetbeless, compilers allow a soHware engineer to

18、easily achieve a good optimization level of the code. Anothcr limitation, which is common to both FPGi\-hased and DSP-hased embedded systems , is the lack of a good user interface. Several video imaging applications

19、 rcqui[C user interaction so a aUI should be provided. The system presented in this papc:r was designed to overcome the above-mentioned limitations prov iding: (i) an embedded device that has both processing power and a

20、Ilexihle GUI; (ii) a sotlware environment in which a developer can easi Iy implement imagc­processing algorithms. The apparatus is a 'stand-alone ' board able to capture, process and play back video si

21、gnals in rea 1-time. The input section can capture a video signal from an analog sourcc, such as a camcorder or a VCR, in both monochromatic and color modes. The data arc then processed by a high perf orman

22、ce digital signal processor, which allows the system to execute in real-time complex imaging algorithms. The video output is displayed in a GUI and both a mOllse and a keyboard arc availahle 10 interact with the s

23、ystem. A software environment is also Proceedings of the 3rd Inlernational Symposium on Image and Signal Processing (llld i\n(tlysis (2003) 936 with a large amount of off-the-shelf devices, such as mice, keyboards, har

24、d drives, etc. Finally, a configurable RS232 serial port and a JT AG connection are present. 3. Software environment With the aid of the integrated development environment Code Composer Studio [7], supplied by

25、 Texas Instruments, a software platform was arranged for rapid proto typing of real time video algorithms. The environment is based on DSP/BIOS, a scalable real? time kernel designed specifically for the DSP platform we

26、 used. A multithreading structure with pre?emptive scheduling was implemented. By simply adding a single thread, which has already been optimized as regards the priority of execution, the user code can be integrated with

27、 the environment. 2): Libraries DPS/BIOS Embedded Board TMS320C64 15 Figure 2. The software environment Three modules were integrated in tlie kernel (figure (i) initialization of the on-boards devices .. (ii) drivers.

28、 (iii) scheduling of the threads. The initialization module contains the routines which set-up all the devices present on the board. It runs just once at the system start -up, initializing the video decoder, the U

29、SB host controller, the FPGA, the graphics processor, the analog'I/O subsystem,' as well as all the DSP on-chip peripherals (Timers, External Memory Interfaces, pcr, EDMA and Serial Ports). The driver module con

30、tains the :routines which manage the peripherals activities at run-time. For example, this module controls the mouse movement, the video data capture, the video' data display as well as the analog signals data 1/0.

31、 The scheduling module manages' the .real-time executions of the threads.' Most of the threads are defined in the driver module. ·A 'further thread is available for the user code. The three modules al

32、so implement the data flow, which is schematically depicted in figure 3. The method used is based on a double-buffering scheme: one buffer (capture-buffer) is used to acquire the current frame while a second buffer (proc

33、essing-buffer) contains the previous frame which is made available to the user for elaboration. Both of these buffers are placed in the internal memory of the DSP. The data captured by the video decoder are temporarily s

34、tored in the FIFO memory, as seen in figure 3. When a line of the image is present in the memory, the data are moved to the capture buffer by a OMA transfer (OMA_t). Once all the lines have been moved to the current fram

35、e, that is, when one iniage is complete, the buffers switch and the user code is run on the new data. The user code processes the data and returns them in the output buffer, which can be allocated anywhere in the memory

36、(on? chip, SBSRAM, SDRAM). The output data are then converted into the video output format and moved to the video buffer, located in the SBSRAM, by a DMA transfer (DMA_2). Finally, the data are moved to the playback buff

37、er of the graphics processor through the PCl bus. ON·CHIP MEMORY Capture-Buffer Processing-Buffer ON·CHIPISBSRAM! SDRAM MEMORY Output-Buffer Video-Buffer Video Output Figure 3. Video data flow. The software env

38、ironment was arranged so that both l the thread scheduling and the data flow management are transparent to the user. Our aim was to allow a software engineer to implement the algorithms without dealing with all the probl

39、ems related to the management of the hardware and to the real-time execution. All the user has to do is to think of the algorithm in C, write and link the code to the software platform and then program the board by using

40、 the JT AG port. 4. Results and future work The system was tested using a camcorder as an input video source (figure 4). The images were acquired with a resolution of 512x512 pixels, 8 bit/pixel, 25 frame/sec., a