外文翻譯---at89c51—高性能8位微處理器（俗稱單片機(jī)）

1、<p>　　2000單詞，1萬(wàn)英文字符，3000漢字</p><p>　　High performance eight monolithic integrated circuits AT89C51</p><p>　　Abstract </p><p>　　Introduced by the Beijing integrated circuit

2、design center design, US produce high performance eight monolithic integrated circuits AT89C51 characteristic, structure and operation application method.</p><p>　　Key word： high performance chip encryptio

3、n operation application</p><p>　　Characteristic AT89C51 and the MCS251 series monolithic integrated circuit is completely compatible on the command system and the pin</p><p>　　Internal on-line

4、 has the 4k byte to be possible to duplicate programs scratches quickly writes the program memory</p><p>　　Entire static work, Operating region: 0Hz～ 24MHz;</p><p>　　Three levels of program memo

5、ries encryption;</p><p>　　128×8 position interior RAM;</p><p>　　32 bidirectional inputs output lines;</p><p>　　Two 16 timers □counters;</p><p>　　Five interrupt sou

6、rces, Two levels of severances priorities;</p><p>　　An entire duplex asynchronous serial mouth;</p><p>　　The intermittence and falls the electricity work way.</p><p>　　二 Functional

7、description</p><p>　　Base pin explanation that,</p><p>　　VCC: Power line voltage.</p><p>　　GND: Earth.</p><p>　　P0 mouth: The P0 mouth is 8 leaks the level to lead the

8、way bidirectional I/O，each foot may absorb the 8TTL gate electric current. When the P1 mouth base pin first time writes 1, is defined inputs for High performance resistance. P0 can use in exterior procedure data-carrier

9、 storage, it may define as the data/O, the P1 mouth buffer can receive outputs the 4TTL gate electric current. After the P1 mouth base pin reads in 1, is pulled by the interior in for is high, may serve as the input, the

10、 P1 </p><p>　　P2 mouth: The P2 mouth is in an interior pulls the resistance 8 bidirectional I/O, the P2 mouth buffer may receive, outputs 4 TTL gate electric current, when the P2 mouth is written "1&quo

11、t;, its base pin is pulled by the interior in the resistance to pull high, also as input. And therefore took when input, the P2 mouth base pin is pulled lowly by exterior, output current. This is because in the interior

12、pulls reason. The P2 mouth when uses in exterior program memory or 16 bit addresses exterior data</p><p>　　high eight bit address signal and the control signal.</p><p>　　P3 mouth: The P3 mouth b

13、ase pin is in 8 belts interior pulls the resistance bidirectional I/O, may receive outputs 4 TTL gate electric current. After the P3 mouth reads in "1", they are pulled by the interior in for the high level, an

14、d serves as the input. As input, because exterior under pulls for the low level, the P3 mouth the output current (ILL) this will be because on pulls reason.</p><p>　　The P3 mouth also may take AT89C51 some s

15、pecial function mouths, the following table shows:</p><p>　　The mouth base pin prepares chooses the function</p><p>　　P3.0 RXD (serial loses entrance)</p><p>　　P3.1 TXD (serial outl

16、et)</p><p>　　P3.2/INT0 (external interrupt 0)</p><p>　　P3.3/WR (exterior data-carrier storage writes elects to pass)</p><p>　　P3.7/RD (exterior data-carrier storage reads elects to

17、pass)</p><p>　　At the same time the P3 mouth for glitters the programming and the programming verification receives some control signals.</p><p>　　RST: Replacement input. When the oscillator rep

18、ositions the component, must maintain the RST foot two machines cycles the high level time.</p><p>　　ALE/PROG: When visits exterior memory, the address lock saves the permission the power output to use in th

19、e lock saving the address the status byte. In FLASH programming period, this pin uses in inputting the programming pulse. In usually, the ALE end outputs the pulse signal by the invariable frequency period, this frequenc

20、y for oscillator frequency 1/6. Therefore it may serve as to exterior output pulse or uses in fixed time the goal. However must pay attention: When serves as exterior data-ca</p><p>　　/PSEN: Exterior program

21、 memory gating signal. In takes by exterior program memory refers to the period, each machine cycle two/PSEN is effective. But when visits exterior data-carrier storage, these two effective/The PSEN signal will not appea

22、r.</p><p>　　/EA/VPP: When/When EA maintains the low level, then exterior program memory (0000H-FFFFH), whether no matter has the internal procedure memory. Attention encryption way 1 o'clock,/EA internal

23、 locking is RESET; When/When the EA end maintains the high level, here internal procedure memory. In FLASH programming period, this pin also uses in exerting the 12V programming power source (VPP).</p><p>　　

24、XTAL1: Reverse oscillator amplifier unit input and internal clock active channel input.</p><p>　　XTAL2: Comes from the reverse oscillator output.</p><p>　　AT89C51 is one kind of low loss, the hi

25、gh performance, CMO the eight microprocessors, Internal on-line has the 4k byte to be possible to duplicate programs scratches quickly writes the degree memory quickly, Can duplicate reads in □the cleaning to solve 1,000

26、 times, The data retention time is ten years. It and MCA 251 The series monolithic integrated circuit is completely</p><p>　　compatible on the command system and the pin, Not only may replace the MCS251 seri

27、es monolithic integrated circuit completely, Moreover can enable the system to have many MCS251 series product no function. AT89C51 may constitute the genuine monolithic integrated circuit smallest application system, In

28、crease system reliability, Reduced the system cost. So long as the procedure length is smaller than 4k, Four I/O provides completely to the user. May use the 5V voltage to program, Moreover scratche</p><p>　

29、　三 Base pin function</p><p>　　The AT89C51 monolithic integrated circuit is 40 pins chips like chart 1 shows. </p><p>　　1) I/O line: P0, P1, P2, P3 the altogether four eight mouths P0 mouth is th

30、e three states of matter bidirectional mouth, Is generally called the data bus mouth。Because is the time sharing output, Therefore should add the latch in exterior to save this address data lock, The address lock saves t

31、he signal to use AL E.</p><p>　　The P1 mouth is specially for user use I/O, Is the bidirectional mouth.</p><p>　　The P2 mouth is from the system expansion when makes the high 8 address wires to

32、use. When does not expand exterior memory, P also may take the user I/O line use, The P2 mouth also is the bidirectional mouth.</p><p>　　The P3 mouth is the double function mouth, This mouth each may indepen

33、dently define as the first I/O function or the second I/O function. As when first function use operates with the P1 mouth. The P3 mouth second function is as follows。</p><p>　　2) Controls the mouth line: PS

34、EN (outside piece takes control), AL E (address lock saves control),</p><p>　　EA (outside piece accumulator choice), RE2SET (replacement control);</p><p>　　3) Power source and clock: CCC, V SS;

35、 XTAL 1, XTAL 2</p><p>　　4 operating procedures</p><p>　　1) Program memory encryption the AT89C51 chip program memory has three levels of hardware encryptions, Can effectively guarantee the sys

36、tem is not imitated and the software is not duplicated, Encryption rank establishment like table 2</p><p>　　2) Working pattern</p><p>　　AT89C51 has the intermittence and fall the electricity tw

37、o kinds of working patterns. The intermittent pattern is establishes by the software, When the periphery component still was at the working mode active status, CPU may at the right moment enter the sleep condition accord

38、ing to the working condition, Internal RAM and all special registers value will maintain。This kind of condition may by any severance institute 62 semiconductors technologies in August, 1997 4th issue，All rights reserved.

39、 Th</p><p>　　3. Oscillators characteristics:</p><p>　　XTAL1 and XTAL2 respectively be reverse amplifier input and output. This reverse amplifier may dispose is the internal oscillator. The stone

40、 crystal vibration and the ceramics vibrate may use. Like uses exterior clock source actuation component, XTAL2 should not meet. Has-odd input to the internal clock signal to have through two frequency divisions triggers

41、, therefore does not have any request to exterior clock signal pulse width, but must guarantee the pulse the height level request width.</p><p>　　4. Chips cleanings:</p><p>　　The entire PEROM ar

42、ray and three locks localizations electricity cleaning may through the correct control signal combination, and maintains the ALE base pin to be in low level 10ms to complete. Scratches in the operation in the chip before

43、, the code array is all written "1" also in any non- spatial memory byte duplicates programs, this operation must carry out. In addition, AT89C51 is equipped with the stable state logic, may in lower to the zer

44、o frequency rate condition under the static logic, </p><p>　　5) Model application</p><p>　　AT89C51 solidification and cleaning operation typical connection like chart 2 show.</p><p&g

45、t;<b>　　Reference</b></p><p>　　1 The MCS251 series monolithic integrated circuit application system design system disposition with meets</p><p>　　Mouth technology, Beijing aerospace u

46、niversity publishing house publication</p><p>　　AT89C51—高性能8位微處理器（俗稱單片機(jī)）</p><p><b>　　摘要 </b></p><p>　　由北京集成電路設(shè)計(jì)中心引進(jìn)，美國(guó)生產(chǎn)的高性能8位單片機(jī)的特性、結(jié)構(gòu)和操作應(yīng)用方法。</p><p>

47、　　關(guān)鍵詞：高性能芯片 加密 操作使用</p><p>　　特性 AT89C51與MCS251系列單片機(jī)的指令系統(tǒng)和管腳完全兼容</p><p>　　內(nèi)部有4k字節(jié)能夠快速編程和擦除程序存儲(chǔ)器 </p><p>　　全靜態(tài)工作，工作范圍：0Hz~24MHz</p><p>　　4 三級(jí)程序存儲(chǔ)器鎖定</p><p&g

48、t;　　5 128×8位內(nèi)部RAM</p><p>　　6 32]可編程I/O</p><p>　　7 兩個(gè)16位定時(shí)器/計(jì)數(shù)器</p><p>　　8 5個(gè)中斷源，兩級(jí)中斷優(yōu)先級(jí)</p><p>　　9 可編程串行通道</p><p>　　10 低功耗的閑置和掉電模式.</p>&l

49、t;p><b>　　二 功能描述 </b></p><p><b>　　基準(zhǔn)引腳說(shuō)明</b></p><p><b>　　VCC：供電電壓</b></p><p><b>　　GND：接地 </b></p><p>　　P0口：P0口為一個(gè)8位漏級(jí)

50、開路雙向I/O口，每腳可吸收8TTL門電流。當(dāng)P0口的管腳第一次寫1時(shí)，被定義為高阻輸入。P0能夠用于外部程序數(shù)據(jù)存儲(chǔ)器，它也可以定義為數(shù)據(jù)I/O，P1口緩沖器能接收輸出4TTL門電流。P1口管腳寫入1后，被內(nèi)部上拉為高，可用作輸入，P1口被外部下拉為低電時(shí)，將輸出電流，這是由于內(nèi)部上拉的緣故。在FLASH編程和校驗(yàn)時(shí)，P1口作為低八位地址接收。</p><p>　　P2口：P2口為一個(gè)內(nèi)部上拉電阻的8 位雙向I

51、/O線，P2口緩沖器可接受、輸出4TTL門電流，當(dāng)P2口被寫入“1”時(shí)，其管腳被內(nèi)部上拉電阻拉高，且作為輸入。并因此作為輸入時(shí),P2口由外部拉低，輸出電流。這是由于內(nèi)部上拉電阻的原因。當(dāng)P2口用于外部程序存儲(chǔ)器或16位地址外部數(shù)據(jù)載體存儲(chǔ)時(shí)，P2口送出高8位地址數(shù)據(jù)。當(dāng)生成地址“1”時(shí)，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，當(dāng)進(jìn)行讀寫外部八位地址數(shù)據(jù)載體存儲(chǔ)器時(shí)，P2口輸出其特殊功能寄存器的內(nèi)容。FLASH編程或校驗(yàn)時(shí)，P2亦接收高位地址

52、和其他控制信號(hào)。</p><p>　　P3口：P3口是一組帶有內(nèi)部上拉電阻的8位雙向I/O口?？山邮蛰敵?TTL門電流。當(dāng)P3口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入。作為輸入，由于外部下拉為低電平，P3口輸出電流這是由于上拉的緣故。</p><p>　　P3口還作AT89C51的一些其他功能引腳，如下圖所示：</p><p><b>　　口管腳

53、備選功能</b></p><p>　　P3.0 RXD (串行輸入口)</p><p>　　P3.1 TXD (串行輸出口)</p><p>　　P3.2/INT0（外部中斷0）</p><p>　　P3.3/WR(外部數(shù)據(jù)存儲(chǔ)器寫選通)</p><p>　　P3.7/RD（外部數(shù)據(jù)存儲(chǔ)器讀選通）.<

54、/p><p>　　P3口同時(shí)作為閃爍編程和編程校驗(yàn)接收一些控制信號(hào)。</p><p>　　RST: 復(fù)位輸出。當(dāng)振蕩器復(fù)位器件時(shí)，要保持RST腳；兩個(gè)機(jī)器周期的高電平時(shí)間。</p><p>　　ALE/PROG: 當(dāng)訪問(wèn)外部?jī)?chǔ)存器時(shí)，地址鎖存保存功率輸出權(quán)限用于鎖定地址的狀態(tài)字節(jié)。在FLASH編程期間，此引腳用于輸入編程脈沖。通常，ALE端以不變的頻率周期輸出脈沖信號(hào)，

55、此頻率為振蕩器頻率的1/6.因此，它可用作對(duì)外部輸出的脈沖或用于定時(shí)目的。然而，需要注意的是，當(dāng)其用作外部數(shù)據(jù)存儲(chǔ)器時(shí)，將會(huì)跳過(guò)一個(gè)ALE脈沖。如想禁止ALE的輸出可在SFR8EH地址設(shè)置0。此時(shí)，ALE只有在執(zhí)行MOVX，MOVC的指令是ALE才能起作用。而且，該引腳被略微拉高。如果微處理器在外部執(zhí)行狀態(tài)ALE禁止，置位無(wú)效。.</p><p>　　/PSEN:外部程序存儲(chǔ)器的選通信號(hào)。在由外部程序存儲(chǔ)器取值期

56、間，每個(gè)機(jī)器周期兩次/PSEN有效。但當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的/PSEN信號(hào)將不出現(xiàn)。</p><p>　　/EA/VPP: 當(dāng)EA處于低電平時(shí)，則在此期間外部程序存儲(chǔ)器（0000H-FFFFH）,不管是否有內(nèi)部程序存儲(chǔ)器。注意加密方式1時(shí)，/EA將內(nèi)部鎖定為REST；當(dāng)EA處于高電平時(shí)，此間內(nèi)部程序存儲(chǔ)器。在FLASH編程期間，此引腳也用于提供12v編程電源（VPP）</p><

57、p>　　XTAL1：反向震蕩放大器的輸入及內(nèi)部時(shí)鐘工作電路的輸入。</p><p>　　XTAL2: 來(lái)自反向振蕩器的輸出。</p><p>　　AT89C51是一種低電壓，高性能CMOS8位單片機(jī)，片內(nèi)4k字節(jié)的可反復(fù)擦寫的只讀程序存儲(chǔ)器，1000次擦寫周期，數(shù)據(jù)保留時(shí)間為10年。它與MCS251系列單擊片的指令系統(tǒng)和引腳完全兼容。不僅能代替MCS251系列單片機(jī)，而且，能使系統(tǒng)擁

58、有MCS251系列單片機(jī)沒(méi)有的功能。AT89C51可能構(gòu)成真正單片機(jī)集成電路最小應(yīng)用系統(tǒng)，增加系統(tǒng)可靠性，降低了系統(tǒng)成本。只要程序長(zhǎng)度小于4k字節(jié)，四個(gè)I/O完全提供給客戶?？捎?v電壓進(jìn)行編程，而且可擦除編寫時(shí)間只需10毫秒，只有8751與87C51清洗時(shí)間的1%，擦除與8751和875C1相比，需12v電壓，不容易損壞部件。不是兩種電源請(qǐng)求時(shí)且不能從芯片上重寫時(shí)，適合多插入類型控制域。工作電壓范圍寬度為2.7v~6v,.全靜態(tài)工作：

59、0Hz~24MHz,</p><p>　　且51系列6MHz~12MHz，與8751和87出1相比更具有靈活性。該系統(tǒng)能夠快速地減速。AT89C51能夠提供三個(gè)級(jí)別的程序記憶加密，提供方便靈活且可靠的硬件加密方法，完全可以保證沒(méi)有被模仿過(guò)的過(guò)程或系統(tǒng)。此外，AT89C51單片機(jī)也有MCA251系列單片機(jī)的所有優(yōu)點(diǎn)，128×8位內(nèi)部RAM,32可編程I/O線，兩個(gè)16位定時(shí)器/計(jì)數(shù)器，兩個(gè)級(jí)別的中斷優(yōu)先級(jí)

60、，一個(gè)全雙工串行通信口及時(shí)鐘發(fā)生器等等。</p><p><b>　　三 引腳功能 </b></p><p>　　AT89C51單片機(jī)的40個(gè)引腳如表格1所示：</p><p>　?。?）I/O線：共有四口分別為P0,P1，P2，P3口，每個(gè)口有8位（8根引腳）P0口是三種狀態(tài)的物質(zhì)雙向口，通常被稱為數(shù)據(jù)總線復(fù)用口。因?yàn)槭菚r(shí)間共享輸出，因此添加

61、外部保存地址時(shí)會(huì)保存數(shù)據(jù)地址，地址鎖存信號(hào)使用ALE。.</p><p>　　P1口是專為用戶使用I/O線的雙向口。.</p><p>　　P2口當(dāng)輸出高8位地址時(shí)擴(kuò)展系統(tǒng)而用。當(dāng)不擴(kuò)展外部存儲(chǔ)器時(shí)，P 也可能需要用戶使用I/O線，P2口也是物質(zhì)雙向口。</p><p>　　P3口是雙功能口，這個(gè)口可獨(dú)立定義作為I/O的第一個(gè)功能或I/O的第二個(gè)功能。當(dāng)一個(gè)功能與P

62、1口一起運(yùn)轉(zhuǎn)時(shí)，P3口的第二個(gè)功能如下：</p><p>　　（2）控制口線：PSEN(程序儲(chǔ)存允許)，ALE（地址鎖存控制）</p><p>　　EA(外部訪問(wèn)允許)，RESET(復(fù)位控制)</p><p>　　3) 電源和時(shí)鐘：CCC: 調(diào)整圖形設(shè)置，VSS：源代碼控制系統(tǒng)：XTAL1：片內(nèi)振蕩器的反相放大器輸入端:XTAL2:內(nèi)振蕩器的反相放大器輸出

63、端</p><p><b>　　四 運(yùn)行程序 </b></p><p>　　1) 程序內(nèi)存加密：AT89C51芯片程序存儲(chǔ)器具有三個(gè)層次的硬件加密，可有效地保證系統(tǒng)沒(méi)有被模仿和軟件不會(huì)重復(fù)，加密位保護(hù)功能如表2</p><p><b>　　2)工作模式</b></p><p>　　AT89C51有

64、閑置模式和掉電模式。閑置模式由軟件建立，根據(jù)工作狀況，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變，這種狀況可能出現(xiàn)在在62半導(dǎo)體協(xié)會(huì)在1997年4月8號(hào)這一期的報(bào)刊上。所有權(quán)利保留，終止或通過(guò)硬件復(fù)位。掉電模式是Vcc處于較低工作電平，振蕩器停止工作，CPU停止執(zhí)行指令。該芯片RAM中的內(nèi)容及全部特殊功能寄存器是不可用的。只有在Vcc恢復(fù)到正常工作電平前，振蕩器重新啟動(dòng)并穩(wěn)定工作，才能

65、退出掉電模式。</p><p><b>　　3）振蕩器特性：.</b></p><p>　　XTAL1和XTAL2分別為反向放大器的輸入和輸出，這種反向的放大器可配置為內(nèi)部振蕩器。石英晶體或陶瓷諧振器可用。像使用外部時(shí)鐘源驅(qū)動(dòng)組件時(shí)，XTAL2應(yīng)不滿足。產(chǎn)生了奇怪的內(nèi)部時(shí)鐘的輸入信號(hào)通過(guò)兩個(gè)頻率分裂觸發(fā)器，因此沒(méi)有任何外部時(shí)鐘信號(hào)脈沖的要求，但必須保證脈沖寬度要求的最

66、高水平。</p><p><b>　　4）芯片擦除：</b></p><p>　　整個(gè)PEROM陣列和三個(gè)鎖定位的電擦除可通過(guò)正確的控制信號(hào)組合，并保持ALE管腳處于低電平10ms來(lái)完成。在芯片操作中，代碼陣列全被寫“1”且在任何非空存儲(chǔ)字節(jié)被重復(fù)編程以前該操作必須被執(zhí)行。此外，AT89C51設(shè)有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。

67、在閑置模式下，CPU停止工作。但RAM，定時(shí)器，計(jì)數(shù)器，串口和中斷系統(tǒng)仍在工作。在掉電模式下，保存RAM的內(nèi)容并且凍結(jié)振蕩器，禁止使用其他芯片工作，直到下一個(gè)硬件復(fù)位為止。</p><p>　　5) 模型應(yīng)用程序.</p><p>　　AT89C51的凝固和清洗作業(yè)的典型連接如圖二所示</p><p><b>　　附注</b></p>