單片機(jī)籃球計(jì)分器畢業(yè)論文中英文資料外文翻譯文獻(xiàn)

1、 單片機(jī) 片機(jī)籃球計(jì)分器外文翻 分器外文翻譯一 英文原文 英文原文：DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The devic

2、e is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolit

3、hic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features: ? Compatible with MCS-51? Products? 4K Bytes of In-Syst

4、em Reprogrammable Flash Memory? Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz? Three-Level Program Memory Lock? 128 x 8-Bit Internal RAM? 32 Programmable I/O Lines? Two 16-Bit Timer/Counter

5、s ? Six Interrupt Sources ? Programmable Serial Channel? Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/count

6、ers, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and su

7、pports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents

8、 but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage. GND Ground.Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output por

9、t each pin can Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device.ALE/PROG Addre

10、ss Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a c

11、onstant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation c

12、an be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the mic

13、rocontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cyc

14、le, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memo

15、ry locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives t

16、he 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2 Output fr

17、om the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Fig

18、ure Port pin alternate functionsP3.0 rxd (serial input port)P3.1 txd (serial output port)P3.2 ^int0 (external interrupt0)P3.3 ^int1 (external interrupt1)P3.4 t0 (timer0 external input)P3.5 t1 (timer1 external input)P3.6