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1、2250 英文單詞, 英文單詞,1.1 萬(wàn)英文字符,中文 萬(wàn)英文字符,中文 3550 字文獻(xiàn)出處: 文獻(xiàn)出處:Raheja J L , Subramaniyam S , Chaudhary A . Real-time hand gesture recognition in FPGA[J]. Optik - International Journal for Light and Electron Optics, 2016, 127(20)
2、:9719-9726.Real-time hand gesture recognition in FPGAJagdish Lal Raheja, Shriram Subramaniyam, Ankit ChaudharyAbstractHand Gesture has been used in different applications and also implemented on different platforms. A fa
3、ster and smooth approach with reasonable accuracy is always needed to make smart devices smarter and faster. This paper describes a novel procedure of hand gesture recognition using Principal Component Analysis (PCA) imp
4、lemented in FPGA Simulator. The simulation was done using co-simulation tool of Simulink with Xilinx System Generator (XSG). Hardware-Software co-simulation is a good methodology which assures accurate and rapid prototyp
5、ing leading to faster simulation times for heterogeneous systems design. Total processing time for the designed hardware was found to be 530 ns using FPGA having the operating frequency of 100 MHz.Keywords: PCA; Hand ges
6、tures recognition ;FPGA; Operating frequency; System clock1. IntroductionThese days Hand gesture is a common way to handle mobile phones, gadgets etc but computers still have a long way to go before they can interact wit
7、h users in a truly natural fashion. The most natural way to interact with a computer from a user’s perspective would be that computer understands all natural gestures. It’s already two decades passed since the developmen
8、t of input devices, but there have not been many changes to initial prototypes; so people often find the interaction with computers an uncomfortable experience. The technology should adapt computers to our natural means
9、of communication. The means of communicating with computers at the moment are limited to a keyboard, mouse, light pen, trackball, keypad etc. These devices have grown to be familiar but inherently limit the speed and nat
10、uralness with which one interact with the computer.Recently, there has been a surge in interest in recognizing human hand gestures. Gesture recognition is a form of biometric identification that relies on data acquired f
11、rom the gesture of an individual. This data, which can be either two-dimensional or three-dimensional in nature, was compared against a precompiled database. Hand gesture recognition has various applications like compute
12、r games, robotic control, Sign language recognition and as an alternative to conventional mouse hardware. Recently hand gesture recognition catches the peak attention of the research in both software and hardware environ
13、ment.PCA is one of the successful techniques used in image compression and object recognition. It is a way of identifying patterns in data and expressing the data in such a way as to highlight their similarity and differ
14、ences. Since it is sometimes difficult to find patterns in data of high dimension [1] PCA has many advantages compared to traditional model-based techniques that rely on geometric features. It has also been used in many
15、machine vision applications such as facial recognition. FPGA is most suited for implementation of real-time image processing algorithm [2–6] and can be readily designed with custom parallel digital circuitry tailored for
16、 performing various image tasks making them well-suited for high-speed real-time vision processing systems.detection method in real time using two cameras.3. Hardware implementationSimulink based Xilinx System Generator
17、was used to implement the hardware on FPGA. In traditional design, the designer was responsible for generating all clocks but in system generator, the task of deriving multiple clocks was removed from the designer by def
18、ault [19]. The algorithm has been implemented for a database (DB) of 6 images initially. The MATLAB code produced 6 × 6 projection vectors and stored in the RAM of the FPGA. After formation of the DB, the system was
19、 made to capture an image and projection vector of 6 × 1 size was produced which was given to the hardware for further process. The hardware was made to be capable of calculating the Euclidian Distance (ED) with a d
20、edicated block, named as ED block. Then the Minimum Distance (MD) was found using a dedicated block named MD block.Fig. 2 shows the co-simulation hardware that is the overall architecture which is having internally the R
21、AM block, ED Block, and MD block. FPGA receive a matrix named ‘projectedimages’ (6 × 6) from MATLAB workspace. The hardware was built in such a way that the test vector was always available until the total execution
22、 completes. The functions of each basic block given in [20] are utilized to build the complete structure.Fig. 2. The complete architecture3.1. Euclidean distance blockThe Euclidean distance between the target projection
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